Every constraint, covergroup, and class library stands on the language core. Types, arrays, procedural scheduling, expressions, compilation, and interfaces form the substrate beneath them.
You need basic Verilog first: modules, assign, clocked always blocks and vectors. Start Here has a two-minute check. By the end of this part you can write a small self-checking testbench that uses the right types, containers and timing.
Topic | Path | Lessons | What it covers | Time |
|---|---|---|---|---|
Required | 5 | How 4-state and 2-state types, nets, casting, and composite types fit together. | 40 min | |
Required | 4 | Four array families, when each one fits, and where to find every lesson. | 30 min | |
Required | 5 | Procedural code and scheduling: the always family, assignments, tasks, regions, startup and flow control. | 40 min | |
Recommended | 5 | Hub — signedness, equality flavors, unique/priority, shifts and streaming, and the width rules that silently corrupt results. | 40 min | |
Required | 5 | Packages, imports, compilation order, parameters and namespace rules for scalable testbenches. | 40 min | |
Required | 4 | Bundle bus signals into one port, add direction views, and sample and drive race-free. | 30 min |
Path: Required is the core first pass for this part's goal, a self-checking testbench; Recommended is what most learners should read; Optional is reference, specialist or revision material to return to later. Each topic hub labels its own lessons.
Types: 4-state against 2-state, nets against variables, and the three casts.
Arrays: packed, queues and dynamic arrays, and associative arrays for scoreboards.
Procedural: always_ff with nonblocking assignments, always_comb, and tasks versus functions.
Sharing: one package of types, a filelist in dependency order, and one interface with a clocking block.
Strings, Reals & Special Types: when you need real models or DPI handles.
The region details in The Event Scheduler (#0, final): when you debug a race.
Shifts, Concatenation & Streaming: when you pack or byte-swap data.
Namespace Hygiene at Scale: when a bench imports several packages.
logic bus that carries X into an int variable hide bugs?An int is 2-state and cannot represent X, so the unknown bits become 0. The checking code then compares a value that looks legal but is really unknown. Keep boundary signals 4-state and check for X explicitly before converting.
Five questions that cover this part. Each answer names the lesson that teaches it.
int and the check passes. Which lesson explains why, and what is the guard?4-State vs 2-State Types: the copy turns X into 0. Check $isunknown before copying into a 2-state variable.
An associative array keyed by ID, taught in Associative Arrays. A queue only fits in-order checking.
d with = at @(posedge clk) and the flop sometimes captures the new value. What is the fix?Drive with a nonblocking assignment, so the update commits in NBA after the flop has sampled. Blocking vs Nonblocking Assignments shows the race.
Compile order and compilation-unit scope: put the typedef in a package and list it first in the filelist. See Compilation Units & Compile Order.
It changes when testbench code samples and drives pins (pre-edge sampling, skewed driving); the DUT is untouched. See Clocking Blocks.