Course map
- 5 lessons
Starts with Who This Course Is For
- 28 lessons
Starts with 4-State vs 2-State Types
- 30 lessons
Starts with Class Declaration & Objects
- 39 lessons
Starts with rand vs randc
- 41 lessons
Starts with Immediate vs Concurrent Assertions
- 25 lessons
Starts with Covergroup Anatomy
- 24 lessons
Starts with The Layered Testbench
- 26 lessons
Starts with DPI Imports
- 23 lessons
Starts with Failure Triage Method
- 34 lessons
Starts with Policy Classes
About this course
Choose a learning path
This course takes SystemVerilog from language foundations to senior verification interviews and principal-level verification. It covers object-oriented testbenches, constraint randomization, assertions, functional coverage, and coverage-driven sign-off.
New to the course? Begin with Start Here: who the course is for, how to run the examples, the words you will meet, and the PacketFIFO project you build along the way.
Choose your path
The course has about 275 lessons, and nobody needs all of them. Pick the row that sounds like you. Every part marks each topic and lesson Required, Recommended or Optional, so you always know what a first pass needs.
Path | Choose this if | Go through |
|---|---|---|
Core SystemVerilog | You write RTL or simple testbenches and want the language, not a full verification flow. | Foundations, OOP, then Randomization |
Verification Engineer | Your job is to build and sign off testbenches. | Parts 1 to 7: Foundations, OOP, Randomization, SVA, Coverage, Testbench, then Advanced as your project needs |
SVA and Coverage | You mainly write assertions and coverage models. | The Foundations lessons on 4-state types, equality, the always blocks and scheduling regions, then SVA and Coverage |
UVM Preparation | You will learn UVM next. | Parts 1 to 6, then the Testbench Bridge to UVM, then the UVM course |
Senior / Interview | You already verify and are preparing for senior interviews or reviews. | Senior & Interview Prep, with the Q&A bank as revision practice |
Principal / Advanced | You lead verification and want depth, judgment and a large capstone. | Principal-Level Verification, an advanced track that assumes the Senior path or equivalent experience |
Start Here and nine parts
Part | Topics | Lessons | Content |
|---|---|---|---|
1 | 5 | Prerequisites and paths, running examples, a glossary, the testbench picture, and the course project. | |
6 | 28 | Types, arrays, procedural code, operators, packages, and interfaces. | |
6 | 30 | Classes, inheritance, virtual interfaces, IPC, and testbench patterns. | |
7 | 39 | rand, constraint operators, solver control, arrays, debug, and drills. | |
8 | 41 | Sequences, properties, sampled values, protocols, debug, and drills. | |
5 | 25 | Covergroups, bins, crosses, options, and closure strategy. | |
5 | 24 | Layering, stimulus, monitors, scoreboards, regression, and UVM bridge. | |
7 | 26 | DPI-C, bind, macros, plusargs, performance, and RTL/TB boundaries. | |
5 | 23 | Debug playbook, review checklists, strategy, Q&A bank, FIFO capstone. | |
6 | 34 | Reusable architecture, out-of-order checking, assertion depth, coverage models, an out-of-order capstone, and judgment. |
How this was checked
Runnable listings carry a self-checking testbench with a PASS line and are run with Verilator 5.048 or Icarus Verilog 13.
Listings the free tools cannot run say what is missing, and are never shown with invented output.
Check yourself You already write directed Verilog testbenches. Which part should you start with?
Part 2 (OOP), after a quick look at Start Here. Who This Course Is For lists three paths.