Plan about 40 minutes for the whole part: roughly 25 minutes of reading and 15 minutes running the examples yourself. It does not teach SystemVerilog yet. It sets you up so the rest of the course reads easily.
Lesson | You will | Path |
|---|---|---|
Check you have the Verilog you need, and pick a path. | Required | |
Run an example, read its verdict, and break it on purpose. | Required | |
Learn twelve must-know words; look up the rest when you meet them. | Recommended | |
See the four jobs every self-checking testbench does. | Required | |
Meet the design you will verify, piece by piece, through the course. | Recommended |
Required is the core first pass for this part. Recommended is something most learners should read. Optional is reference, specialist or revision material that you can skip on a first pass (this part has none).
Whether your Verilog is enough, and which of the six paths fits you.
How to run an example and read its PASS or FAIL line.
The four jobs of a self-checking testbench.
The twelve must-know words.
The look-up words in Words You Will Meet: come back when a lesson uses one.
The PacketFIFO table: come back at each part to see what you add next.
The path you did not pick: revisit it when your goal changes.
No. This course teaches the SystemVerilog that UVM is built from. The UVM course comes after it.
Answer these five without scrolling up. Each answer names the lesson that teaches it.
Modules, assign, clocked always blocks with reset, if/case with nonblocking assignment, and vector widths. RTL Foundations teaches them; Who This Course Is For has the readiness check.
No. Only a PASS line with exit status 0 is a pass, and a good bench has been seen to FAIL once. Taught in How the Lessons and Examples Work.
A driver puts values on the DUT inputs; a monitor only watches pins and rebuilds transactions. Taught in Words You Will Meet.
Stimulus, reference model, checker, verdict. Taught in The Testbench Picture.
A header (kind, dest, len), len payload bytes and a check byte marked last; the check byte is the XOR of the bytes before it, so a whole packet XORs to 0. Taught in The PacketFIFO Project.