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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
    • Senior Debug Playbook
      • Failure Triage Method
      • Waveform Debug Strategy
      • Debugging the Testbench
      • Hunting X's and Races
    • Reviewing Verification Code
    • Verification Strategy: Spec to Sign-Off
    • SystemVerilog Interview Q&A Bank
    • Capstone: Verify a Parameterized FIFO
  • Principal-Level Verification34
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←Senior & Interview Preparation
  1. Topics
  2. SystemVerilog
  3. Senior & Interview Preparation
  4. Senior Debug Playbook

Part 8 of 9Part 8 of 9/Senior & Interview PrepIntermediate

Senior Debug Playbook

Triage, waveform, testbench, and X and race methods with worked cases for senior debug.

  • 4topics
  • 4lessons

Senior debug is a loop: triage the failure, shrink it to a minimal repro, hypothesize one cause, and run the cheapest experiment that falsifies it. Only the first error matters, the testbench is the prime suspect, and every fix leaves a regression behind.

Diagram
Legend: [TRIAGE] [WAVE] [TB] [X/RACE]

  THE DEBUG LOOP — every failure goes through this cycle

  failure report
       │
       ▼
  ┌─────────────────────┐
  │ 1. TRIAGE [TRIAGE]   │  first error only · classify signature
  │    where to look?    │  TB bug? RTL bug? spec ambiguity?
  └─────────┬───────────┘
            ▼
  ┌─────────────────────┐
  │ 2. REPRODUCE         │  same seed · same build · minimal test
  │    shrink the case   │  shorter sim · fewer agents · one txn
  └─────────┬───────────┘
            ▼
  ┌─────────────────────┐
  │ 3. HYPOTHESIZE       │  one suspect at a time
  │    cheapest test?    │  log? assertion? wave? code read?
  └─────────┬───────────┘
            ▼
  ┌─────────────────────┐
  │ 4. EXPERIMENT        │  waves [WAVE] · TB instrumentation [TB]
  │    falsify it        │  X-trace [X/RACE] · directed re-run
  └─────────┬───────────┘
            ▼
     hypothesis survives? ──no──► back to 3 with new evidence
            │ yes
            ▼
     fix + add a regression test that would have caught it

Lesson

What it covers

Path

Failure Triage Method

First-error discipline, six signature classes, and the testbench versus RTL verdict.

Required

Waveform Debug Strategy

Backward tracing, first-divergence markers, sampler pitfalls, and a monitor case.

Required

Debugging the Testbench

Activity gates, loud failures, hang triage, and two testbench cases.

Recommended

Hunting X's and Races

First-X back-propagation, reset audits, race protocol, and a gate-level case.

Recommended

Path: Required is the core first pass for this topic, Recommended is what most learners should read, and Optional is reference, specialist or revision material you can skip at first.

Check yourself A log holds 200 errors after one scoreboard mismatch. Which error do you debug first, and why?

The first one. Everything after it ran in a corrupted state, so later errors are usually echoes of the original fault.

Interviewers probe method, not tools: first-error discipline, a verdict backed by pin-level evidence, and one war story with a generalized lesson. This topic gives you all three.

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See also

  • Reviewing Verification Code
  • Verification Strategy: Spec to Sign-Off
  • SystemVerilog Interview Q&A Bank