This part is an optional integration track. It covers the places where a testbench meets C code, RTL you do not own, the build system and simulator limits, and you do not need all of it. Pick the topics your project needs, read those, and come back for the rest when a project asks.
If your project... | Read | Why |
|---|---|---|
checks RTL that someone else owns | Checkers attach without editing the design files. | |
runs many tests from one compiled image | Knobs and seeds change per run, with no recompile. | |
sees a value that is off by one cycle, or results that differ between tools | Races and clocking blocks explain both. | |
has a reference model written in C | Call the tested C code instead of copying it. | |
shares build files or one library across teams | Defines and guards keep the build predictable. | |
has a slow or memory-hungry regression | Measure first, then fix the biggest cost. |
Topic | Lessons | What it covers | Time | Path |
|---|---|---|---|---|
4 | DPI-C links SystemVerilog testbenches to C models through imports, exports, and shared data. | 30 min | Optional | |
5 | Bind checkers into RTL without editing it: syntax, modules, files, libraries, and debug. | 40 min | Required | |
4 | Text macros, conditional compilation, include guards, and macro debugging for reliable builds. | 30 min | Recommended | |
4 | One image, many runs: plusargs, files, config objects, memory images and wave control. | 30 min | Required | |
4 | Where simulation time and memory go, and the measurement discipline that keeps regressions fast. | 30 min | Optional | |
4 | Where testbench meets RTL: races, clocking blocks, scheduling regions and safe cross-boundary access. | 30 min | Recommended | |
1 | Optional reference: which randomization, assertion and coverage features Verilator 5.048 and Icarus 13 run correctly, reject, or get wrong. | 20 min | Optional |
Required is the core first pass for this part's goal, attaching checks and running many tests, Recommended is for most learners, and Optional is reference, specialist or revision material you can skip until a project needs it.
Bind Fundamentals and Writing Assertion Modules for bind: the PacketFIFO checker lives here.
$test$plusargs & $value$plusargs and Config Architecture: depth and seed per run.
Anatomy of a TB/RTL Race and Clocking Blocks as the Cure: the one bug every testbench meets.
DPI-C, all four lessons: when a C reference model or a C library appears in your project.
Macros and compilation: when the build breaks, or when you write a shared include file.
Performance and memory: when a regression gets slow, or a soak run runs out of memory.
Bind File Organization, Include Guards, Hierarchical References and Force/Release, Exports and Context: specialist pages, for big environments and legacy code.
The bound instance elaborates inside the RTL's own scope, so an output or an internal drive would change the design without anyone reviewing it. Taught in Writing Assertion Modules for bind.
No. Counts and seeds are plusargs read at run time, so one image serves every run. A FIFO depth is a parameter and is fixed at build time. Taught in $test$plusargs & $value$plusargs.
Sample through a clocking block, which reads in the Preponed region, the value the flop captured. Taught in Clocking Blocks as the Cure.
The tested C code stays the single source of truth, and a second copy can drift. Taught in DPI Imports.
ifdef on a misspelled define builds without a warning. What did the build do?It silently took the false branch, because an undefined name is simply false. Taught in Conditional Compilation.