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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
    • SystemVerilog Data Types
    • Arrays: Packed, Dynamic, Queues & Associative
    • Procedural Code & Scheduling
      • always_comb, always_ff, always_latch
      • Blocking vs Nonblocking Assignments
      • Tasks vs Functions
      • The Event Scheduler & Stratified Regions
      • Loops & Flow Control
    • Operators, Expressions & Width Rules
    • Packages, Typedefs & Compilation
    • Interfaces, Modports & Clocking Blocks
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
  • Principal-Level Verification34
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←SystemVerilog Language Foundations
  1. Topics
  2. SystemVerilog
  3. SystemVerilog Language Foundations
  4. Procedural Code & Scheduling

Part 1 of 9Part 1 of 9/Language FoundationsIntermediate

Procedural Code & Scheduling

Procedural code and scheduling: the always family, assignments, tasks, regions, startup and flow control.

  • 5topics
  • 5lessons

Procedural code runs inside a discrete-event scheduler: at each simulation time it works through a fixed order of regions, and that order decides which value every statement sees.

This topic starts with the blocks and assignments you write every day, then opens the scheduler itself in The Event Scheduler.

Lesson

Path

What it covers

always_comb, always_ff, always_latch

Required

Intent contracts, sensitivity including functions, and the latch-inference fix.

Blocking vs Nonblocking Assignments

Required

Two schedules, the swap classic, shift pipelines, and RTL and testbench rules.

Tasks vs Functions

Required

The time rule, automatic storage, and argument directions including ref.

The Event Scheduler & Stratified Regions

Recommended

Regions in one time slot, #0, $display versus $strobe, and deterministic startup. First pass: skim the diagrams and the $display versus $strobe rule.

Loops & Flow Control

Recommended

Loop shapes, break, continue and disable, and timing controls in forever.

Path: Required is the core first pass for this part's goal, a self-checking testbench; Recommended is what most learners should read; Optional is reference, specialist or revision material to return to later.

Check yourself A flop samples d at a clock edge while the testbench drives a new d with <= at the same edge. Which value does the flop take, and in which region does the drive commit?

The flop takes the pre-edge value. A nonblocking drive commits in the NBA region, after every Active-region sample has finished. A blocking = drive at that edge would be a race instead.

Scheduling questions are staples at every level: the two-register swap, what #0 really does, and why two initial blocks can race. Each lesson below carries one such question with its answer.

PreviousNext: always_comb, always_ff, always_latch

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See also

  • SystemVerilog Data Types
  • Arrays: Packed, Dynamic, Queues & Associative
  • Operators, Expressions & Width Rules