SystemVerilog expressions look like C but evaluate by their own rules. Signedness, operand width and X propagation follow the language reference manual, even when the result surprises.
Five rules cause most of the surprises: signedness, X in comparisons, checked case claims, shifts and packing, and the width an expression is computed at. Each lesson below takes one of them and proves it in simulation.
Lesson | Path | What it proves |
|---|---|---|
Recommended | The compare bug, the | |
Required | Which equality to use, why | |
Recommended | Checked branch claims that replaced the old synthesis pragmas. | |
Optional | Sign-preserving shifts, unsigned concats and one-line byte reversal. Optional on a first pass: streaming is a specialist tool for packing and byte order. | |
Recommended | The |
Path: Required is the core first pass for this part's goal, a self-checking testbench; Recommended is what most learners should read; Optional is reference, specialist or revision material to return to later.
Case equality, ===. It compares X and Z literally and always returns 0 or 1, while == returns X when an X bit leaves the answer open. The equality lesson shows all three operators side by side.