What you need first

The course assumes you can read basic Verilog. You do not need to know any SystemVerilog, classes or verification yet.

If any row is new, take RTL Foundations first. It teaches exactly these, and it uses the same kind of runnable examples.

A two-minute readiness check

Read the counter and its testbench below. The testbench drives the inputs, waits for clock edges, and checks the output twice.

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module count4 (
  input  wire       clk,
  input  wire       rst,
  input  wire       en,
  output reg  [3:0] q
);
  always @(posedge clk)
    if (rst)     q <= 4'd0;
    else if (en) q <= q + 4'd1;
endmodule

module tb_count4;
  reg clk = 0, rst = 1, en = 0;
  wire [3:0] q;
  integer errors = 0;
  count4 dut (.clk(clk), .rst(rst), .en(en), .q(q));
  always #5 clk = ~clk;
  initial begin
    @(negedge clk) rst = 0;
    @(negedge clk) en = 1;
    repeat (3) @(negedge clk);
    if (q !== 4'd3) errors = errors + 1;   // first check
    en = 0;
    repeat (2) @(negedge clk);
    if (q !== 4'd3) errors = errors + 1;   // second check
    if (errors == 0) $display("PASS: count4 counted 3 enabled edges and held while disabled");
    else $fatal(1, "FAIL: count4 ended at %0d", q);
    $finish;
  end
endmodule

PASS: count4 counted 3 enabled edges and held while disabled

This is the output the simulator printed:

PASS: count4 counted 3 enabled edges and held while disabled

If you could follow the timing and got 3 before revealing the answer, you are ready. If negedge, repeat or !== was unclear, the first lessons of Part 1 cover the SystemVerilog parts, and RTL Foundations covers the Verilog parts.

Pick a path

Choose the row that matches your goal. Each path lists real lessons, in the order to read them. You can switch paths later: every lesson stands on its own.

Core SystemVerilog

• Part 1 · Language Foundations: data types, operators, procedural code, arrays, interfaces, packages

• Part 2 · Object-Oriented SystemVerilog: classes, handles, inheritance, virtual interfaces

• Part 3 · Randomization: rand, constraints, seeding

Verification Engineer

• Parts 1 to 3 as above.

• Part 4 · Assertions and Part 5 · Functional Coverage

• Part 6 · Advanced Language and Integration: bind, plusargs, races, DPI-C

• Part 7 · Testbench Architecture: generator, driver, monitor, scoreboard, regression

SVA and Coverage

• Prerequisites: 4-State vs 2-State Types, Equality, Case Equality and Wildcards, always_comb, always_ff, always_latch and The Event Scheduler and Stratified Regions

• Part 4 · Assertions

• Part 5 · Functional Coverage, after Enums, Structs and Unions

UVM Preparation

• Parts 1 to 6: Foundations, OOP, Randomization, Assertions, Coverage, Advanced

• From Hand-Built TB to UVM: concept mapping, what UVM automates, migration strategy

• Then the UVM course.

Senior / Interview

• Part 8 · Senior and Interview Preparation: debug playbook, code review, verification strategy, capstone FIFO

• Revision drills: Interview Q&A Bank. Dip back into a part when a question exposes a gap.

Principal / Advanced

• Part 9 · Principal-Level Verification: assertion depth, coverage modelling, reusable architecture, out-of-order checking, judgment, capstone

• Assumes the Senior path or equivalent experience.

Related topics

• Next: How the Lessons and Examples Work

• RTL Foundations