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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
    • SystemVerilog Data Types
    • Arrays: Packed, Dynamic, Queues & Associative
      • Packed vs Unpacked Arrays
      • Dynamic Arrays and Queues
      • Associative Arrays
      • Array Methods and Selection
    • Procedural Code & Scheduling
    • Operators, Expressions & Width Rules
    • Packages, Typedefs & Compilation
    • Interfaces, Modports & Clocking Blocks
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
  • Principal-Level Verification34
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←SystemVerilog Language Foundations
  1. Topics
  2. SystemVerilog
  3. SystemVerilog Language Foundations
  4. Arrays: Packed, Dynamic, Queues & Associative

Part 1 of 9Part 1 of 9/Language FoundationsIntermediate

Arrays: Packed, Dynamic, Queues & Associative

Four array families, when each one fits, and where to find every lesson.

  • 4topics
  • 4lessons

SystemVerilog has four array families. Packed arrays are single bit vectors, fixed unpacked arrays are collections of elements, dynamic arrays and queues are sized at runtime, and associative arrays are sparse maps keyed by value.

Five shapes, one question each: is the size fixed, does it grow, is the index sparse?

Family

Declaration

Size

Synthesizable

Packed

logic [7:0] bus

Fixed at compile time

Yes

Unpacked fixed

logic [7:0] mem [0:255]

Fixed at compile time

Yes

Dynamic

int data[]

new[n] at runtime

No, testbench only

Queue

int q[$]

Grows per push

No, testbench only

Associative

byte mem [longint]

One entry per written key

No, testbench only

Lesson

Path

You will build…

Packed vs unpacked

Required

Layout, slicing and copy rules that infer RAM instead of flops.

Dynamic arrays and queues

Required

Runtime sizing plus an in-order checker built on a queue.

Associative arrays

Required

A sparse memory and an out-of-order checker keyed by ID.

Array methods and selection

Recommended

Reductions, finders, sorting, and picking the right container. Recommended because scoreboards use find, sort and unique, but you can look the methods up as you need them.

Path: Required is the core first pass for this part's goal, a self-checking testbench; Recommended is what most learners should read; Optional is reference, specialist or revision material to return to later.

Check yourself A testbench must model a 64-bit address space but touches a few hundred locations. Which family fits, and why not a fixed array?

An associative array keyed by address. It allocates storage only for written keys. A fixed array of 2^64 bytes is impossible to allocate.

“Compare the four array families” is a stock verification question. Know one sentence per family: packed is one vector, fixed unpacked is N elements, dynamic is sized once at runtime, queues stream, associative maps sparse keys.

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See also

  • SystemVerilog Data Types
  • Procedural Code & Scheduling
  • Operators, Expressions & Width Rules