GPU Design · All levels

SM Architecture Overview

Shader Multiprocessor & Core Pipeline: An SM integrates warp schedulers, register files, execution units, caches, and control logic; balance between these blocks determines sustainable throughput.

What this topic teaches

SM Architecture Overview converts GPU architecture concepts into review-ready engineering decisions. An SM integrates warp schedulers, register files, execution units, caches, and control logic; balance between these blocks determines sustainable throughput. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.

The senior-engineer question

When SM IPC, functional-unit utilization, and front-end bubble ratio shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?

diagram

SIMT EXECUTION — SM Architecture Overview

warp 0 lanes:  0 1 2 3 4 5 6 7 ... 31
active mask :  1 1 1 1 0 0 1 1 ...  1
instruction :  IF branch taken on active lanes

cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges

Focus: anchor discussion in lane masks and warp progress
Metric tracked: SM IPC, functional-unit utilization, and front-end bubble ratio

Picture the architecture

Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.

SM datapath skeleton

diagram

SM BLOCK DIAGRAM — SM Architecture Overview

        +---------------------------+
        | Warp Schedulers / Dispatch|
        +------------+--------------+
                     |
     +---------------+----------------+
     |  Register File / Operand Cross |
     +--------+---------------+-------+
              |               |
           [ALU/FPU]       [LD/ST]
              |               |
              +-------+-------+
                      |
                L1 / Shared Mem

Focus: from scheduler to RF to ALU/LDST to shared/L1

Architecture ownership split

diagram

GPU OWNERSHIP LAYERS — SM Architecture Overview

artifact area     owner
----------------  ----------------------------
architecture    GPU architect
RTL/microarch   SM RTL owner
software/tools  performance modeling lead

Rule: each metric needs a named owner before signoff.

SM and datapath context

diagram

SM BLOCK DIAGRAM — SM Architecture Overview

        +---------------------------+
        | Warp Schedulers / Dispatch|
        +------------+--------------+
                     |
     +---------------+----------------+
     |  Register File / Operand Cross |
     +--------+---------------+-------+
              |               |
           [ALU/FPU]       [LD/ST]
              |               |
              +-------+-------+
                      |
                L1 / Shared Mem

Focus: front-end to execute dataflow

Memory hierarchy context

diagram

GPU MEMORY HIERARCHY — SM Architecture Overview

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: capacity vs latency

Scheduler context

diagram

WARP SCHEDULER VIEW — SM Architecture Overview

cycle ->      0    1    2    3    4
eligible   [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued         W1      W2    W7      W7    W3
stall reason    -    dep wait  -   mem wait  -

Scheduler objective: keep issue slots non-empty.
Focus: eligible warp quality

Ownership layers

diagram

GPU OWNERSHIP LAYERS — SM Architecture Overview

artifact area     owner
----------------  ----------------------------
architecture    GPU architect
RTL/microarch   SM RTL owner
software/tools  performance modeling lead

Rule: each metric needs a named owner before signoff.

Evidence to collect

Primary metric: SM IPC, functional-unit utilization, and front-end bubble ratio.
Primary artifact: SM block diagram, utilization heatmap, and issue-stage pipeline trace.
Owners to include: GPU architect, SM RTL owner, performance modeling lead.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.

Roofline lens

diagram

BANDWIDTH ROOFLINE — SM Architecture Overview

performance
   ^
   |                compute ceiling
   |               /
   |              /
   |-------------/------------------ memory ceiling
   +------------------------------------------> operational intensity
      memory-bound             compute-bound

Interpretation: identify compute vs memory bound

Coalescing lens

diagram

COALESCING PATTERN — SM Architecture Overview

WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C    -> contiguous -> 1 transaction segment

lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58  -> strided/scatter -> many segments

Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatter

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.

Key takeaways

Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.

Common pitfalls

Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.

GPU deep dive

Shader-core throughput is gated by issue policy, register-bank access, and pipeline hazard behavior.

Concept diagram

diagram

SM CORE LOOP

warp schedulers -> issue ports -> ALU/FPU/Tensor pipelines
scoreboard + register file gate progress

Metric graph

diagram

SM BOTTLENECK MIX

dependency stalls   ███████
bank conflicts      ████
pipeline bubbles    ███

Reports and artifacts

SM IPC dashboard
issue stall taxonomy
register-bank conflict log
shader unit utilization

Mini case study

Compiler register allocation shifted operand banking, doubling RF conflicts and causing a 14% shader regression.

Debug branches

Inspect scoreboard wait-depth trends
Track RF conflicts by instruction class
Separate front-end issue loss from backend saturation

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.

Practice this lesson