GPU Memory Hierarchy

Section goal

Registers, shared memory, caches, and VRAM access behavior, with emphasis on coalescing and bandwidth efficiency.

How to study this section

1. Start with each topic hub and sketch the SIMT-to-silicon mechanism.

2. Use reports and debug pages to prove bottlenecks with evidence.

3. Practice worked examples and interview drills for design-review fluency.

4. Close with checklist and silicon impact before signoff claims.

Topics

1. register-and-shared-memory/ - Register & Shared Memory

2. l1-cache-and-texture/ - L1 Cache & Texture Path

3. l2-and-last-level-cache/ - L2 & Last-Level Cache

4. global-vram-coalescing/ - Global VRAM Coalescing

Related topics

• GPU Design course hub

GPU deep dive

Bandwidth wins come from coalescing and locality discipline, not peak-memory specs alone.

Concept diagram

MEMORY HIERARCHY

register -> shared/L1 -> L2/LLC -> HBM/GDDR
access pattern quality decides latency

Metric graph

BANDWIDTH UTILIZATION

requested BW  ███████████
effective BW  ████████
wasted BW     ███

Reports and artifacts

• L1/L2 hit-rate report

• HBM efficiency counters

• coalescing transaction log

• shared-memory bank audit

Mini case study

Stencil kernel sat at 43% of peak HBM due to uncoalesced loads; layout rewrite recovered 1.6x effective bandwidth.

Debug branches

• Check transactions per request at warp granularity

• Classify cache-thrash versus true DRAM saturation

• Audit shared-memory bank conflicts before algorithm rewrites

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?