Shader Multiprocessor & Core Pipeline

Section goal

SM microarchitecture, ALU/FPU datapaths, register-file constraints, and issue-scoreboard behavior that shape IPC.

How to study this section

1. Start with each topic hub and sketch the SIMT-to-silicon mechanism.

2. Use reports and debug pages to prove bottlenecks with evidence.

3. Practice worked examples and interview drills for design-review fluency.

4. Close with checklist and silicon impact before signoff claims.

Topics

1. sm-architecture-overview/ - SM Architecture Overview

2. shader-alu-and-fpu-pipeline/ - Shader ALU & FPU Pipeline

3. register-file-banking/ - Register File Banking

4. instruction-issue-and-scoreboard/ - Instruction Issue & Scoreboard

Related topics

• GPU Design course hub

GPU deep dive

Shader-core throughput is gated by issue policy, register-bank access, and pipeline hazard behavior.

Concept diagram

SM CORE LOOP

warp schedulers -> issue ports -> ALU/FPU/Tensor pipelines
scoreboard + register file gate progress

Metric graph

SM BOTTLENECK MIX

dependency stalls   ███████
bank conflicts      ████
pipeline bubbles    ███

Reports and artifacts

• SM IPC dashboard

• issue stall taxonomy

• register-bank conflict log

• shader unit utilization

Mini case study

Compiler register allocation shifted operand banking, doubling RF conflicts and causing a 14% shader regression.

Debug branches

• Inspect scoreboard wait-depth trends

• Track RF conflicts by instruction class

• Separate front-end issue loss from backend saturation

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?