Graphics Pipeline Architecture

Section goal

Front-end to back-end graphics flow including geometry expansion, rasterization, fragment shading, and tile-based designs.

How to study this section

1. Start with each topic hub and sketch the SIMT-to-silicon mechanism.

2. Use reports and debug pages to prove bottlenecks with evidence.

3. Practice worked examples and interview drills for design-review fluency.

4. Close with checklist and silicon impact before signoff claims.

Topics

1. vertex-tessellation-geometry-stages/ - Vertex, Tessellation & Geometry Stages

2. rasterization-and-early-z/ - Rasterization & Early-Z

3. fragment-shader-and-rops/ - Fragment Shader & ROPs

4. tile-based-deferred-rendering/ - Tile-Based Deferred Rendering

Related topics

• GPU Design course hub

GPU deep dive

Frame-time stability depends on balancing fixed-function stages with programmable shader pressure.

Concept diagram

GRAPHICS PIPELINE

vertex -> tessellation -> raster -> fragment -> ROP/blend

Metric graph

FRAME-TIME PRESSURE

fragment shading load  ████████
raster backpressure    █████
ROP/blend stalls       ████

Reports and artifacts

• stage occupancy timeline

• early-Z efficiency report

• ROP queue depth

• overdraw heatmap

Mini case study

Async compute overlapped with heavy fragment scenes and triggered ROP queue buildup, causing p99 frame spikes.

Debug branches

• Correlate frame spikes with stage-level queues

• Validate early-Z effectiveness under real content

• Isolate graphics-compute arbitration conflicts

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?