GPU Design · All levels

GPU Design Cheatsheet

Dense reference for SIMT debugging, bottleneck isolation, and architecture review discussions.

Debug order

diagram

WORKLOAD -> BOTTLENECK -> MECHANISM -> ARTIFACT -> OWNER -> DECISION

SIMT: lane masks, divergence, reconvergence
SM: issue slots, scoreboard waits, pipeline utilization
MEMORY: coalescing, cache pressure, bandwidth efficiency
FABRIC: NoC hotspots, controller queues, host/device overlap
SILICON: thermal response, DVFS behavior, timing closure risk

Questions before proposing a fix

Which workload fails first and how reproducible is it?
Is bottleneck compute, memory, interconnect, graphics stage, or thermal?
Which artifact proves the mechanism?
Who owns the minimal reversible fix?
What end-to-end validation gates are required for release?

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