Shader ALU & FPU Pipeline: Comparison Matrix

Comparison matrix

Pipeline width and execution-unit mix trade area, frequency, and workload versatility.

Use the matrix as a decision aid, not as a scoring shortcut. GPU design choices are strongly workload-dependent: the same policy can be correct for dense regular compute, wrong for sparse or divergent kernels, and dangerous for mixed graphics+compute scenes.

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Conservative     | stable closure | lower peak     | new product    |
| Balanced         | good efficiency | needs profiling | broad mix      |
| Aggressive       | max throughput | sensitive tails | premium SKU    |
| Refactor         | scales cleaner | longer cycle   | chronic stalls |
+------------------+----------------+----------------+----------------+

When to choose each approach

• Choose architecture and tuning policy from measured bottleneck mix and product phase

Interview traps

• Copying tactics across unrelated workloads

• Ignoring inter-stage coupling in graphics+compute paths

Evidence comparison

GPU EVIDENCE MATRIX - Shader ALU & FPU Pipeline

+---------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                  | Tells you                      | Does not prove                 | Next action               |
+---------------------------+--------------------------------+--------------------------------+---------------------------+
| occupancy + issue report  | warp residency and issue shape | memory transaction quality     | inspect coalescing        |
| cache + bandwidth counters| hierarchy pressure             | scheduler fairness causes      | profile warp arbitration  |
| lane-mask / branch trace  | divergence and reconvergence   | thermal or voltage stability   | pair with power telemetry |
| NoC/controller snapshots  | congestion and queue hotspots  | source-level mapping quality   | correlate with kernel map |
| release benchmark matrix  | end-to-end workload behavior   | root cause depth               | run focused reproducer    |
+---------------------------+--------------------------------+--------------------------------+---------------------------+

GPU deep dive

Shader-core throughput is gated by issue policy, register-bank access, and pipeline hazard behavior.

Concept diagram

SM CORE LOOP

warp schedulers -> issue ports -> ALU/FPU/Tensor pipelines
scoreboard + register file gate progress

Metric graph

SM BOTTLENECK MIX

dependency stalls   ███████
bank conflicts      ████
pipeline bubbles    ███

Reports and artifacts

• SM IPC dashboard

• issue stall taxonomy

• register-bank conflict log

• shader unit utilization

Mini case study

Compiler register allocation shifted operand banking, doubling RF conflicts and causing a 14% shader regression.

Debug branches

• Inspect scoreboard wait-depth trends

• Track RF conflicts by instruction class

• Separate front-end issue loss from backend saturation

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

• Always pair micro-kernel metrics with end-to-end workload impact.

• Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

• Optimizing occupancy without checking memory-system saturation.

• Comparing profiler captures from different driver or compiler builds.

• Declaring wins without reproducible accuracy and performance gates.

Principal GPU review addendum

Shader ALU & FPU Pipeline is not just a definition to memorize. In a real GPU program it becomes an interaction between software shape, compiler mapping, warp execution, memory movement, interconnect policy, and physical limits. The first senior move is to name which layer is being exercised before interpreting a counter.

Integer and floating-point pipelines have distinct latency/throughput profiles; dependency spacing and dual-issue opportunities drive effective shader performance. This mechanism matters because GPUs are throughput machines: a small inefficiency repeated across lanes, warps, SMs, frames, or dispatches can dominate product performance even when a unit-level diagram looks balanced.

Use ALU/FPU occupancy, pipeline hazard frequency, and instruction latency overlap as an entry point, not as the conclusion. A metric shift only becomes actionable after it is tied to a workload slice, a profiler capture, an architectural path, and a reproducible artifact such as pipeline timing chart, instruction mix breakdown, and hazard replay report.

SM microarchitecture efficiency is set by datapath balance, issue policy, and operand delivery. The review posture is therefore evidence-first: explain what the kernel or graphics workload asked for, how the GPU mapped it onto hardware, where useful work stopped, and which owner can change the smallest boundary safely.

In review, insist on a concrete chain from workload to hardware behavior: workload shape -> compiler/runtime mapping -> warp or pipeline behavior -> memory/fabric pressure -> measured product impact. That chain prevents generic GPU tuning advice from replacing engineering evidence.