GPU Design · All levels

L1 Cache & Texture Path

GPU Memory Hierarchy: L1 and texture caches reduce VRAM traffic for spatially/temporally local accesses; working-set and access stride drive hit quality.

What this topic teaches

L1 Cache & Texture Path converts GPU architecture concepts into review-ready engineering decisions. L1 and texture caches reduce VRAM traffic for spatially/temporally local accesses; working-set and access stride drive hit quality. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.

The senior-engineer question

When L1 hit rate, texture cache efficiency, and cache-thrashing incidents shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?

diagram

SIMT EXECUTION — L1 Cache & Texture Path

warp 0 lanes:  0 1 2 3 4 5 6 7 ... 31
active mask :  1 1 1 1 0 0 1 1 ...  1
instruction :  IF branch taken on active lanes

cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges

Focus: anchor discussion in lane masks and warp progress
Metric tracked: L1 hit rate, texture cache efficiency, and cache-thrashing incidents

Picture the architecture

Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.

L1/texture position in hierarchy

diagram

GPU MEMORY HIERARCHY — L1 Cache & Texture Path

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: show texture path as a locality optimizer before VRAM

Cache-locality roofline lens

diagram

BANDWIDTH ROOFLINE — L1 Cache & Texture Path

performance
   ^
   |                compute ceiling
   |               /
   |              /
   |-------------/------------------ memory ceiling
   +------------------------------------------> operational intensity
      memory-bound             compute-bound

Interpretation: show when improving L1 hit rate shifts a kernel toward compute-bound

SM and datapath context

diagram

SM BLOCK DIAGRAM — L1 Cache & Texture Path

        +---------------------------+
        | Warp Schedulers / Dispatch|
        +------------+--------------+
                     |
     +---------------+----------------+
     |  Register File / Operand Cross |
     +--------+---------------+-------+
              |               |
           [ALU/FPU]       [LD/ST]
              |               |
              +-------+-------+
                      |
                L1 / Shared Mem

Focus: front-end to execute dataflow

Memory hierarchy context

diagram

GPU MEMORY HIERARCHY — L1 Cache & Texture Path

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: capacity vs latency

Scheduler context

diagram

WARP SCHEDULER VIEW — L1 Cache & Texture Path

cycle ->      0    1    2    3    4
eligible   [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued         W1      W2    W7      W7    W3
stall reason    -    dep wait  -   mem wait  -

Scheduler objective: keep issue slots non-empty.
Focus: eligible warp quality

Ownership layers

diagram

GPU OWNERSHIP LAYERS — L1 Cache & Texture Path

artifact area     owner
----------------  ----------------------------
architecture    memory system lead
RTL/microarch   graphics architect
software/tools  driver team

Rule: each metric needs a named owner before signoff.

Evidence to collect

Primary metric: L1 hit rate, texture cache efficiency, and cache-thrashing incidents.
Primary artifact: cache hit/miss profile, access stride study, and texture-path latency report.
Owners to include: memory system lead, graphics architect, driver team.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.

Roofline lens

diagram

BANDWIDTH ROOFLINE — L1 Cache & Texture Path

performance
   ^
   |                compute ceiling
   |               /
   |              /
   |-------------/------------------ memory ceiling
   +------------------------------------------> operational intensity
      memory-bound             compute-bound

Interpretation: identify compute vs memory bound

Coalescing lens

diagram

COALESCING PATTERN — L1 Cache & Texture Path

WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C    -> contiguous -> 1 transaction segment

lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58  -> strided/scatter -> many segments

Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatter

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.

Key takeaways

Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.

Common pitfalls

Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.

GPU deep dive

Bandwidth wins come from coalescing and locality discipline, not peak-memory specs alone.

Concept diagram

diagram

MEMORY HIERARCHY

register -> shared/L1 -> L2/LLC -> HBM/GDDR
access pattern quality decides latency

Metric graph

diagram

BANDWIDTH UTILIZATION

requested BW  ███████████
effective BW  ████████
wasted BW     ███

Reports and artifacts

L1/L2 hit-rate report
HBM efficiency counters
coalescing transaction log
shared-memory bank audit

Mini case study

Stencil kernel sat at 43% of peak HBM due to uncoalesced loads; layout rewrite recovered 1.6x effective bandwidth.

Debug branches

Check transactions per request at warp granularity
Classify cache-thrash versus true DRAM saturation
Audit shared-memory bank conflicts before algorithm rewrites

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.

Practice this lesson