GPU Design · All levels
L2 & Last-Level Cache
GPU Memory Hierarchy: A shared L2/LLC smooths off-chip traffic and inter-client sharing, but contention and policy choices can shift bottlenecks across engines.
What this topic teaches
L2 & Last-Level Cache converts GPU architecture concepts into review-ready engineering decisions. A shared L2/LLC smooths off-chip traffic and inter-client sharing, but contention and policy choices can shift bottlenecks across engines. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.
The senior-engineer question
When L2 hit ratio, eviction pressure, and inter-SM coherence traffic shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?
SIMT EXECUTION — L2 & Last-Level Cache
warp 0 lanes: 0 1 2 3 4 5 6 7 ... 31
active mask : 1 1 1 1 0 0 1 1 ... 1
instruction : IF branch taken on active lanes
cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges
Focus: anchor discussion in lane masks and warp progress
Metric tracked: L2 hit ratio, eviction pressure, and inter-SM coherence trafficPicture the architecture
Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.
Shared cache choke points
GPU MEMORY HIERARCHY — L2 & Last-Level Cache
[ Registers ]
latency: 1-2 cycles
|
[ Shared/L1 ]
latency: 20-40 cycles
|
[ L2 ]
latency: 150-250 cycles
|
[ HBM/GDDR VRAM ]
latency: 300ns+ effective
Optimization lens: explain cross-SM traffic concentration at L2/LLCEviction and contention root cause tree
ROOT-CAUSE TREE — L2 & Last-Level Cache
L2 hit ratio, eviction pressure, and inter-SM coherence traffic regressed
|
reproducible on replay?
/ \
no yes
| |
env/test noise counter triage
|
compute-bound or memory-bound?
/ \
compute memory/interconnect
issue stalls cache/NoC/DRAM stalls
Stop at first failing mechanism, then patch.SM and datapath context
SM BLOCK DIAGRAM — L2 & Last-Level Cache
+---------------------------+
| Warp Schedulers / Dispatch|
+------------+--------------+
|
+---------------+----------------+
| Register File / Operand Cross |
+--------+---------------+-------+
| |
[ALU/FPU] [LD/ST]
| |
+-------+-------+
|
L1 / Shared Mem
Focus: front-end to execute dataflowMemory hierarchy context
GPU MEMORY HIERARCHY — L2 & Last-Level Cache
[ Registers ]
latency: 1-2 cycles
|
[ Shared/L1 ]
latency: 20-40 cycles
|
[ L2 ]
latency: 150-250 cycles
|
[ HBM/GDDR VRAM ]
latency: 300ns+ effective
Optimization lens: capacity vs latencyScheduler context
WARP SCHEDULER VIEW — L2 & Last-Level Cache
cycle -> 0 1 2 3 4
eligible [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued W1 W2 W7 W7 W3
stall reason - dep wait - mem wait -
Scheduler objective: keep issue slots non-empty.
Focus: eligible warp qualityOwnership layers
GPU OWNERSHIP LAYERS — L2 & Last-Level Cache
artifact area owner
---------------- ----------------------------
architecture memory system lead
RTL/microarch GPU architect
software/tools NoC owner
Rule: each metric needs a named owner before signoff.Evidence to collect
Primary metric: L2 hit ratio, eviction pressure, and inter-SM coherence traffic.
Primary artifact: L2 traffic breakdown, eviction reason chart, and bandwidth pressure summary.
Owners to include: memory system lead, GPU architect, NoC owner.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.
Roofline lens
BANDWIDTH ROOFLINE — L2 & Last-Level Cache
performance
^
| compute ceiling
| /
| /
|-------------/------------------ memory ceiling
+------------------------------------------> operational intensity
memory-bound compute-bound
Interpretation: identify compute vs memory boundCoalescing lens
COALESCING PATTERN — L2 & Last-Level Cache
WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C -> contiguous -> 1 transaction segment
lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58 -> strided/scatter -> many segments
Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatterSubpages in this topic
Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.
Key takeaways
Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.
Common pitfalls
Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.
GPU deep dive
Bandwidth wins come from coalescing and locality discipline, not peak-memory specs alone.
Concept diagram
MEMORY HIERARCHY
register -> shared/L1 -> L2/LLC -> HBM/GDDR
access pattern quality decides latencyMetric graph
BANDWIDTH UTILIZATION
requested BW ███████████
effective BW ████████
wasted BW ███Reports and artifacts
L1/L2 hit-rate report
HBM efficiency counters
coalescing transaction log
shared-memory bank audit
Mini case study
Stencil kernel sat at 43% of peak HBM due to uncoalesced loads; layout rewrite recovered 1.6x effective bandwidth.
Debug branches
Check transactions per request at warp granularity
Classify cache-thrash versus true DRAM saturation
Audit shared-memory bank conflicts before algorithm rewrites
Senior review question
Ask: which metric and benchmark pairing proves this topic is truly closed in production context?
Key takeaways
Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.
Common pitfalls
Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.