SM Array Floorplanning: Review Checklist

Review checklist

Review Checklist for SM Array Floorplanning centers on wirelength, congestion density, and frequency vs area tradeoff. The objective is to connect profiler evidence to root-cause mechanism and release-safe action.

• Workload scope and target KPI are explicitly documented.

• Profiler + counter evidence is reproducible with revision tags.

• Bottleneck classification is proved with mechanism-level traces.

• Mitigation includes owner, blast radius, and rollback criteria.

• End-to-end benchmark matrix confirms closure.

• Owners signed: physical design lead, GPU architect, implementation owner.

Signoff ownership

GPU OWNERSHIP LAYERS — SM Array Floorplanning

artifact area     owner
----------------  ----------------------------
architecture    physical design lead
RTL/microarch   GPU architect
software/tools  implementation owner

Rule: each metric needs a named owner before signoff.

GPU deep dive

GPU PPA closure must co-optimize floorplan locality, IR stability, thermal headroom, and timing margin.

Concept diagram

GPU PD VIEW

HBM edges + SM clusters + cache rings + power/clock grid

Metric graph

CLOSURE PRESSURE

timing risk        ███████
thermal risk       █████
IR transients      ████

Reports and artifacts

• SM-array congestion map

• thermal hotspot report

• IR drop during burst load

• timing closure dashboard

Mini case study

A floorplan iteration improved routing but worsened hotspot density, forcing DVFS throttling in sustained workloads.

Debug branches

• Map critical paths to floorplan and thermal zones

• Run burst-current IR checks, not only static IR

• Tie DVFS behavior back to physical hotspot evidence

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

• Always pair micro-kernel metrics with end-to-end workload impact.

• Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

• Optimizing occupancy without checking memory-system saturation.

• Comparing profiler captures from different driver or compiler builds.

• Declaring wins without reproducible accuracy and performance gates.

Review checklist explanation

A checklist is not bureaucracy here; it is how GPU teams avoid confusing local wins with product wins. Every signoff item should protect against a known class of false confidence.

For SM Array Floorplanning, the minimum checklist is workload scope, wirelength, congestion density, and frequency vs area tradeoff, artifact evidence (macro floorplan snapshot, congestion map, and placement tradeoff study), bottleneck classification, owner, rollback path, and full matrix validation.

If the change affects architecture or RTL, include correctness and PPA evidence. If it affects compiler/runtime policy, include compatibility and deployment evidence. If it affects physical design, include timing, IR, thermal, and observability evidence.