GPU Design · All levels
SM Array Floorplanning
GPU Physical Design & Power: SM arrays, caches, and memory interfaces must be floorplanned for locality and routability while preserving timing and power distribution quality.
What this topic teaches
SM Array Floorplanning converts GPU architecture concepts into review-ready engineering decisions. SM arrays, caches, and memory interfaces must be floorplanned for locality and routability while preserving timing and power distribution quality. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.
The senior-engineer question
When wirelength, congestion density, and frequency vs area tradeoff shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?
SIMT EXECUTION — SM Array Floorplanning
warp 0 lanes: 0 1 2 3 4 5 6 7 ... 31
active mask : 1 1 1 1 0 0 1 1 ... 1
instruction : IF branch taken on active lanes
cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges
Focus: anchor discussion in lane masks and warp progress
Metric tracked: wirelength, congestion density, and frequency vs area tradeoffPicture the architecture
Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.
SM array floorplan heuristic
GPU FLOORPLAN (ABSTRACT)
+------------+ +------------+ +------------+ +------------+
| SM0 | | SM1 | | SM2 | | SM3 |
+------------+ +------------+ +------------+ +------------+
| | /
+---------+------ L2 / NoC spine -------+
|
memory controller edge
Objective: minimize critical wirelength while keeping routability balanced.Physical design ownership layers
GPU OWNERSHIP LAYERS — SM Array Floorplanning
artifact area owner
---------------- ----------------------------
architecture physical design lead
RTL/microarch GPU architect
software/tools implementation owner
Rule: each metric needs a named owner before signoff.SM and datapath context
SM BLOCK DIAGRAM — SM Array Floorplanning
+---------------------------+
| Warp Schedulers / Dispatch|
+------------+--------------+
|
+---------------+----------------+
| Register File / Operand Cross |
+--------+---------------+-------+
| |
[ALU/FPU] [LD/ST]
| |
+-------+-------+
|
L1 / Shared Mem
Focus: front-end to execute dataflowMemory hierarchy context
GPU MEMORY HIERARCHY — SM Array Floorplanning
[ Registers ]
latency: 1-2 cycles
|
[ Shared/L1 ]
latency: 20-40 cycles
|
[ L2 ]
latency: 150-250 cycles
|
[ HBM/GDDR VRAM ]
latency: 300ns+ effective
Optimization lens: capacity vs latencyScheduler context
WARP SCHEDULER VIEW — SM Array Floorplanning
cycle -> 0 1 2 3 4
eligible [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued W1 W2 W7 W7 W3
stall reason - dep wait - mem wait -
Scheduler objective: keep issue slots non-empty.
Focus: eligible warp qualityOwnership layers
GPU OWNERSHIP LAYERS — SM Array Floorplanning
artifact area owner
---------------- ----------------------------
architecture physical design lead
RTL/microarch GPU architect
software/tools implementation owner
Rule: each metric needs a named owner before signoff.Evidence to collect
Primary metric: wirelength, congestion density, and frequency vs area tradeoff.
Primary artifact: macro floorplan snapshot, congestion map, and placement tradeoff study.
Owners to include: physical design lead, GPU architect, implementation owner.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.
Roofline lens
BANDWIDTH ROOFLINE — SM Array Floorplanning
performance
^
| compute ceiling
| /
| /
|-------------/------------------ memory ceiling
+------------------------------------------> operational intensity
memory-bound compute-bound
Interpretation: identify compute vs memory boundCoalescing lens
COALESCING PATTERN — SM Array Floorplanning
WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C -> contiguous -> 1 transaction segment
lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58 -> strided/scatter -> many segments
Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatterSubpages in this topic
Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.
Key takeaways
Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.
Common pitfalls
Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.
GPU deep dive
GPU PPA closure must co-optimize floorplan locality, IR stability, thermal headroom, and timing margin.
Concept diagram
GPU PD VIEW
HBM edges + SM clusters + cache rings + power/clock gridMetric graph
CLOSURE PRESSURE
timing risk ███████
thermal risk █████
IR transients ████Reports and artifacts
SM-array congestion map
thermal hotspot report
IR drop during burst load
timing closure dashboard
Mini case study
A floorplan iteration improved routing but worsened hotspot density, forcing DVFS throttling in sustained workloads.
Debug branches
Map critical paths to floorplan and thermal zones
Run burst-current IR checks, not only static IR
Tie DVFS behavior back to physical hotspot evidence
Senior review question
Ask: which metric and benchmark pairing proves this topic is truly closed in production context?
Key takeaways
Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.
Common pitfalls
Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.