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Clock & Power Domains in GPU

GPU Physical Design & Power: Partitioning into clock/power domains enables frequency and power management but introduces crossing constraints and control complexity.

What this topic teaches

Clock & Power Domains in GPU converts GPU architecture concepts into review-ready engineering decisions. Partitioning into clock/power domains enables frequency and power management but introduces crossing constraints and control complexity. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.

The senior-engineer question

When domain crossing violations, clock skew budget, and power-state transition stability shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?

diagram

SIMT EXECUTION — Clock & Power Domains in GPU

warp 0 lanes:  0 1 2 3 4 5 6 7 ... 31
active mask :  1 1 1 1 0 0 1 1 ...  1
instruction :  IF branch taken on active lanes

cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges

Focus: anchor discussion in lane masks and warp progress
Metric tracked: domain crossing violations, clock skew budget, and power-state transition stability

Picture the architecture

Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.

Clock and power partition map

diagram

CLOCK / POWER DOMAIN MAP

[GPC domain]  [SM array domain]  [L2+MC domain]  [always-on control]
     |               |                 |                 |
   PLL A           PLL B             PLL C            fixed clock

Crossings require CDC synchronizers and reset sequencing aligned to power-state transitions.

Domain crossing and reset triage

diagram

ROOT-CAUSE TREE — Clock & Power Domains in GPU

domain crossing violations, clock skew budget, and power-state transition stability regressed
        |
  reproducible on replay?
      /              \
    no                yes
    |                  |
env/test noise    counter triage
                   |
             compute-bound or memory-bound?
                /                  \
             compute            memory/interconnect
             issue stalls       cache/NoC/DRAM stalls

Stop at first failing mechanism, then patch.

SM and datapath context

diagram

SM BLOCK DIAGRAM — Clock & Power Domains in GPU

        +---------------------------+
        | Warp Schedulers / Dispatch|
        +------------+--------------+
                     |
     +---------------+----------------+
     |  Register File / Operand Cross |
     +--------+---------------+-------+
              |               |
           [ALU/FPU]       [LD/ST]
              |               |
              +-------+-------+
                      |
                L1 / Shared Mem

Focus: front-end to execute dataflow

Memory hierarchy context

diagram

GPU MEMORY HIERARCHY — Clock & Power Domains in GPU

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: capacity vs latency

Scheduler context

diagram

WARP SCHEDULER VIEW — Clock & Power Domains in GPU

cycle ->      0    1    2    3    4
eligible   [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued         W1      W2    W7      W7    W3
stall reason    -    dep wait  -   mem wait  -

Scheduler objective: keep issue slots non-empty.
Focus: eligible warp quality

Ownership layers

diagram

GPU OWNERSHIP LAYERS — Clock & Power Domains in GPU

artifact area     owner
----------------  ----------------------------
architecture    clock architect
RTL/microarch   low-power owner
software/tools  SoC integration lead

Rule: each metric needs a named owner before signoff.

Evidence to collect

Primary metric: domain crossing violations, clock skew budget, and power-state transition stability.
Primary artifact: clock-domain map, power-domain intent spec, and CDC/RDC signoff summary.
Owners to include: clock architect, low-power owner, SoC integration lead.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.

Roofline lens

diagram

BANDWIDTH ROOFLINE — Clock & Power Domains in GPU

performance
   ^
   |                compute ceiling
   |               /
   |              /
   |-------------/------------------ memory ceiling
   +------------------------------------------> operational intensity
      memory-bound             compute-bound

Interpretation: identify compute vs memory bound

Coalescing lens

diagram

COALESCING PATTERN — Clock & Power Domains in GPU

WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C    -> contiguous -> 1 transaction segment

lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58  -> strided/scatter -> many segments

Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatter

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.

Key takeaways

Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.

Common pitfalls

Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.

GPU deep dive

GPU PPA closure must co-optimize floorplan locality, IR stability, thermal headroom, and timing margin.

Concept diagram

diagram

GPU PD VIEW

HBM edges + SM clusters + cache rings + power/clock grid

Metric graph

diagram

CLOSURE PRESSURE

timing risk        ███████
thermal risk       █████
IR transients      ████

Reports and artifacts

SM-array congestion map
thermal hotspot report
IR drop during burst load
timing closure dashboard

Mini case study

A floorplan iteration improved routing but worsened hotspot density, forcing DVFS throttling in sustained workloads.

Debug branches

Map critical paths to floorplan and thermal zones
Run burst-current IR checks, not only static IR
Tie DVFS behavior back to physical hotspot evidence

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.

Practice this lesson