Verification has its own vocabulary, and some words appear before the lesson that teaches them. When that happens, the meaning below is enough to keep reading.
Learn these twelve before Part 1. Everything after them in this lesson is look-up: skim it once and return when a lesson uses a word.
DUT: the design under test, the RTL being checked.
Testbench: code that drives the DUT, checks it and reports a verdict.
Stimulus: the inputs the testbench applies.
Reference model: code that computes the right answer from the spec.
Driver: turns transactions into pin activity on the DUT inputs.
Monitor: watches pins and rebuilds transactions; never drives.
Scoreboard: compares what the monitor saw with what the reference model expected.
Interface: a named bundle of signals connecting testbench and DUT.
Class, object, handle: the type, the thing new builds, and the variable that points at it.
Seed: the starting number of the random generator; the same seed repeats the run.
Assertion: a rule about signals over clock cycles that the simulator checks constantly.
Coverage: a record of which planned scenarios actually happened.
The full tables below say where each word is taught. The twelve must-know words are in bold; the rest are look-up.
Word | One-line meaning | Taught in |
|---|---|---|
DUT | The design under test: the RTL being checked. | |
Testbench | Code that drives the DUT, checks its outputs and reports a verdict. It is not built into hardware. | |
Stimulus | The input values and sequences the testbench applies. | |
Reference model | Code that computes the right answer from the spec, to compare against the DUT. | |
Transaction | One operation described as data, such as one packet or one bus write, instead of as pin wiggles. | |
Driver | The part that turns transactions into pin activity on the DUT inputs. | |
Monitor | The part that watches pins and rebuilds transactions from what happened. It never drives. | |
Scoreboard | The part that compares what the monitor saw with what the reference model expected. |
Word | One-line meaning | Taught in |
|---|---|---|
Interface | A named bundle of signals that connects a testbench to a DUT in one port. | |
Class, object, handle | A class is a type; new builds an object from it at run time; a handle is a variable that points at an object. | |
Virtual interface | A handle to an interface, so class code can reach DUT pins. | |
rand, constraint, randomize() | Fields the solver fills with random values that obey rules you write. | |
Seed | The starting number of the random generator. The same seed repeats the same run. | |
Assertion | A rule about signal behaviour over clock cycles that the simulator checks all the time. | |
Coverage | A record of which planned scenarios actually happened during the runs. | |
Regression | Many tests and seeds run together, with one pass or fail summary. | |
UVM | A standard library of testbench classes built from these same ideas. It has its own course. |
A driver puts values on the DUT inputs. A monitor only watches pins and reports what happened. If a monitor drove anything, the testbench would be checking its own stimulus instead of the DUT.
To know what the right answer is. The scoreboard compares two streams: what the DUT did (from the monitor) and what it should have done (from the reference model).
Every Taught in link was checked against the course page list on 2026-10-18.