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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
  • Principal-Level Verification34
    • Reusable Testbench Architecture
    • Checking Out-of-Order Traffic
    • Assertion Depth
    • Coverage Modelling for Real Features
    • Capstone: Out-of-Order Memory Controller
    • Principal Judgment
      • Escaped Bug Analysis
      • Intermittent Failures
      • Metrics That Lie
      • Scaling Verification
      • System Design Interviews
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←Principal-Level Verification
  1. Topics
  2. SystemVerilog
  3. Principal-Level Verification
  4. Principal Judgment

Part 9 of 9Part 9 of 9/Principal-Level VerificationAdvanced

Principal Judgment

Escaped bugs, intermittent failures, misleading metrics, scaling verification, and system design interviews.

  • 5topics
  • 5lessons

Revision practice: not part of the first pass. The System Design Interviews lesson is interview drilling; the other four lessons are the first pass.

At principal level the hard questions are not about syntax. They are about why a bug got through, whether a failure is real, whether a number can be trusted, and where the next week of effort should go. This topic works through those calls with illustrative cases and small benches you can run and break.

Every case here is a made-up scenario built to teach a pattern. None of them describes a real product or company.

Diagram
THE QUESTIONS A VERIFICATION LEAD ANSWERS

  "A bug reached silicon."      -> which gap let it through?    escaped-bug-analysis
  "It fails on 1 seed in 40."   -> real bug, TB bug, or race?   intermittent-failures
  "Coverage is 100%."           -> 100% of what?                metrics-that-lie
  "We have 6 months and 1 SoC." -> where does each check run?   scaling-verification
  "How would you verify X?"     -> plan, env, checks, closure   system-design-interviews

Lesson

Path

What it covers

Escaped Bug Analysis

Required

Tracing an escape back to plan, stimulus, coverage and checking gaps, and fixing the class of bug, not one instance.

Intermittent Failures

Recommended

Seed- and race-dependent failures, from the first report to the root cause, with a seed-sweep bench.

Metrics That Lie

Recommended

Coverage at 100% with a live bug, flat bug curves and pass-rate traps.

Scaling Verification

Optional

IP versus SoC, reusing checks upward, emulation hand-off, and when gate-level and X-propagation runs pay off.

System Design Interviews

Optional

Walkthroughs for an AXI interconnect, a cache and a DMA engine, with the follow-up questions.

Path says how much of each lesson a first pass needs. Required: core for this topic, read it. Recommended: most learners should read it. Optional: reference, specialist or revision material; skip it on a first pass and return when you need it.

Check yourself A regression is 100% green and coverage is 100%. Name two reasons a serious bug could still be present.

The coverage model may measure what the stimulus or RTL does rather than the features in the spec, so 100% says nothing about the missing corner. And a checker may be blind to the symptom: a scenario can be covered while nothing compares the result against an independent expectation.

Principal interviews nearly always include one open question: "Tell me about a bug that escaped and what you changed." A strong answer names the gap (plan, stimulus, coverage or check), the fix to that gap, and the sweep for the same pattern elsewhere.

Related topics

  • Part 9: Principal-Level Verification

  • Verification Strategy: Spec to Sign-Off

  • Senior Debug Playbook

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See also

  • Reusable Testbench Architecture
  • Checking Out-of-Order Traffic
  • Assertion Depth