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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
  • Principal-Level Verification34
    • Reusable Testbench Architecture
    • Checking Out-of-Order Traffic
    • Assertion Depth
    • Coverage Modelling for Real Features
    • Capstone: Out-of-Order Memory Controller
      • Spec and Plan
      • Executable Spec: One Bench per Rule
      • Environment
      • Environment Self-Test
      • Checking
      • Testing the Checkers
      • Coverage and Closure
      • Merging Runs and Reading Holes
      • Bug Hunt: Six Bugs and the Full Bench
      • Bug Hunt Results and Sign-Off
    • Principal Judgment
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←Principal-Level Verification
  1. Topics
  2. SystemVerilog
  3. Principal-Level Verification
  4. Capstone: Out-of-Order Memory Controller

Part 9 of 9Part 9 of 9/Principal-Level VerificationAdvanced

Capstone: Out-of-Order Memory Controller

Verify a small ID-tagged memory controller end to end in ten lessons: spec and plan, a policy-driven environment, ID and memory checking, coverage closure, and a hunt for six planted bugs.

  • 10topics
  • 10lessons

Capstone map

One story in ten short lessons: each page delivers one artifact, and the next page builds on it. Read them in this order; every bench runs on Verilator 5.048 unless a page says otherwise.

#

Lesson

Path

Delivers

Runnable bench

1

Spec and Plan

Required

Rules R1 to R6, risk ranking, plan rows with done criteria

No

2

Executable Spec

Recommended

The controller and a directed bench with one scenario per rule

Yes

3

Environment

Required

Policy layers, phases, abstract BFMs, bounded drivers

No

4

Environment Self-Test

Recommended

Proof that drivers and monitor agree before any checker is trusted

Yes

5

Checking

Required

Checker ownership per rule, monitor order of work, ID assertion

Not run

6

Testing the Checkers

Recommended

A designless unit test: which checker must fire for each fault

Yes

7

Coverage and Closure

Required

Coverage rows CV1 to CV9, covergroups and cover properties

Not run

8

Merging Runs and Reading Holes

Recommended

A closure curve over ten seeds and the reading of its holes

Yes

9

Bug Hunt: Six Bugs and the Full Bench

Required

The six planted bugs and the complete self-checking bench

Yes

10

Bug Hunt Results and Sign-Off

Recommended

Which checker caught each bug, escapes, the sign-off review and known gaps

No

Path says how much of the lesson a first pass needs. Required: the core of the capstone, read it. Recommended: most learners should read it, because it proves the previous page. Optional: reference, specialist or revision material. Pages 1, 3, 5, 7 and 9 tell the story on their own; the even pages are where it is proven by running it.

This capstone verifies a design with the traits that make senior interviews hard: two request ports, reads that come back out of order across IDs, byte-strobed writes, back-pressure on both sides, and a reset that can land in the middle of traffic. The design is small enough to read in one sitting and real enough to hide bugs.

It reuses the patterns from the earlier topics: policy layers and an abstract BFM from Reusable Testbench Architecture, the ID scoreboard and memory model from Checking Out-of-Order Traffic, and the coverage mirror from Coverage Modelling. Lessons 9 and 10 plant six bugs and show which checker catches each one, and when.

Diagram
port 0 ──req──►┌──────────────────────────┐
  port 1 ──req──►│ ooo_memctl #(BUG)         │──rsp──► sink (back-pressure)
                 │  16-word memory, strobes  │
                 │  8-entry read table       │   in order per {port, id}
                 │  round-robin on contention│   any order across them
                 └──────────────────────────┘
  policy items ─► abstract BFMs ─► pins ─► monitor ─► scoreboard + memory model
                                              ├──► coverage mirror (CV1-CV9)
                                              └──► assertions: fairness, stability, no orphan

The design has a BUG parameter. BUG = 0 is correct; 1 to 6 select an ID swap, a dropped strobe, a lost response after reset, starvation, a duplicate response, and wrong ordering within an ID. Every bench that contains the design passes with BUG = 0 and was run against the planted bugs.

Check yourself The controller answers reads out of order. Why can the scoreboard still use queues instead of searching for a match?

Order is only free across ordering domains. Within one {port, id} the spec promises request order, so each domain gets its own queue and every response is compared with the head of its queue. Searching for a match anywhere would accept a within-ID swap, which is one of the planted bugs.

Likely question: “Walk me through how you would verify an out-of-order memory controller.” A strong answer follows this topic's order: the rules and their risks, a plan with closure criteria, an environment that can reach the risky states, checkers that encode the ordering and memory rules exactly, coverage that proves the states were reached, and evidence that the checkers catch planted bugs.

Related topics

  • Part 9: Principal-Level Verification

  • Part 8 capstone: Parameterized FIFO

  • Previous topic: Coverage Modelling

  • Next topic: Principal Judgment

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See also

  • Reusable Testbench Architecture
  • Checking Out-of-Order Traffic
  • Assertion Depth