GPU Design · All levels

Performance Counters & Debug

Verification, Performance & Bring-up: Hardware counters expose stall reasons, cache behavior, and utilization; correct interpretation links telemetry to actionable microarchitectural fixes.

What this topic teaches

Performance Counters & Debug converts GPU architecture concepts into review-ready engineering decisions. Hardware counters expose stall reasons, cache behavior, and utilization; correct interpretation links telemetry to actionable microarchitectural fixes. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.

The senior-engineer question

When counter fidelity, sampling overhead, and root-cause turnaround time shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?

diagram

SIMT EXECUTION — Performance Counters & Debug

warp 0 lanes:  0 1 2 3 4 5 6 7 ... 31
active mask :  1 1 1 1 0 0 1 1 ...  1
instruction :  IF branch taken on active lanes

cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges

Focus: anchor discussion in lane masks and warp progress
Metric tracked: counter fidelity, sampling overhead, and root-cause turnaround time

Picture the architecture

Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.

Counter-to-root-cause flow

diagram

COUNTER DEBUG FLOW

capture counters -> correlate with timeline -> isolate first anomaly -> replay
      |                    |                          |
  stall reasons         queue depth              mechanism proof

Best practice: combine counters with waveform/trace snapshots, not counters alone.

Measured improvement curve

diagram

BEFORE / AFTER — Performance Counters & Debug

metric quality
  ^
  |                        o target region
  |                 o post-fix validation
  |            o
  |      o baseline (failing)
  +------------------------------------------> iteration
      evidence capture  mechanism fix  closure

Use this to prove improvement is causal, not incidental.

SM and datapath context

diagram

SM BLOCK DIAGRAM — Performance Counters & Debug

        +---------------------------+
        | Warp Schedulers / Dispatch|
        +------------+--------------+
                     |
     +---------------+----------------+
     |  Register File / Operand Cross |
     +--------+---------------+-------+
              |               |
           [ALU/FPU]       [LD/ST]
              |               |
              +-------+-------+
                      |
                L1 / Shared Mem

Focus: front-end to execute dataflow

Memory hierarchy context

diagram

GPU MEMORY HIERARCHY — Performance Counters & Debug

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: capacity vs latency

Scheduler context

diagram

WARP SCHEDULER VIEW — Performance Counters & Debug

cycle ->      0    1    2    3    4
eligible   [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued         W1      W2    W7      W7    W3
stall reason    -    dep wait  -   mem wait  -

Scheduler objective: keep issue slots non-empty.
Focus: eligible warp quality

Ownership layers

diagram

GPU OWNERSHIP LAYERS — Performance Counters & Debug

artifact area     owner
----------------  ----------------------------
architecture    performance engineer
RTL/microarch   driver team
software/tools  silicon debug owner

Rule: each metric needs a named owner before signoff.

Evidence to collect

Primary metric: counter fidelity, sampling overhead, and root-cause turnaround time.
Primary artifact: counter dictionary, profiler capture, and root-cause walkthrough.
Owners to include: performance engineer, driver team, silicon debug owner.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.

Roofline lens

diagram

BANDWIDTH ROOFLINE — Performance Counters & Debug

performance
   ^
   |                compute ceiling
   |               /
   |              /
   |-------------/------------------ memory ceiling
   +------------------------------------------> operational intensity
      memory-bound             compute-bound

Interpretation: identify compute vs memory bound

Coalescing lens

diagram

COALESCING PATTERN — Performance Counters & Debug

WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C    -> contiguous -> 1 transaction segment

lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58  -> strided/scatter -> many segments

Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatter

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.

Key takeaways

Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.

Common pitfalls

Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.

GPU deep dive

Performance claims need verification-grade reproducibility, not one-off profiler screenshots.

Concept diagram

diagram

PERF VERIFICATION LOOP

benchmark -> profile -> optimize -> verify correctness -> regress

Metric graph

diagram

RELEASE READINESS

benchmarks stable     █████████
accuracy gates pass   ████████
perf regressions open ███

Reports and artifacts

golden benchmark suite
deterministic replay log
perf regression dashboard
accuracy/perf gate status

Mini case study

A kernel passed microbenchmarks but failed production SLA due to host-device sync overhead hidden from isolated tests.

Debug branches

Enforce end-to-end benchmarks alongside kernels
Pair every speedup with accuracy diff checks
Promote only reproducible profiler baselines

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.

Practice this lesson