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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
      • Overlap vs Non-Overlap
      • Pure Vacuity
      • Chained Consequent With ##
      • Non-Overlapped Window
      • throughout in Consequent
      • OR Antecedent Trigger
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Implication Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Implication Puzzles
  5. OR Antecedent Trigger
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    VLSI DV Interview PuzzlesAll levels

    OR Antecedent Trigger

    Property intent: if either request source rises, grant must follow one cycle later. Timeline (all other samples are 0): req_a stays 0, req_b rises 0->1 at C40, and grant stays 0 at C41. Determine the verdict.

    Puzzle

    Difficulty: Easy · Puzzle 6 of 6 · Topic: Implication Puzzles

    Property intent: if either request source rises, grant must follow one cycle later. Timeline (all other samples are 0): req_a stays 0, req_b rises 0->1 at C40, and grant stays 0 at C41. Determine the verdict.

    Code

    design.sv
    property p_or_antecedent;
      @(posedge clk) ($rose(req_a) or $rose(req_b)) |-> ##1 grant;
    endproperty

    Hint

    Only one side of the OR needs to trigger the implication.

    Step-by-step solution

    Diagram
    1) At C40, $rose(req_b) is true while $rose(req_a) is false.
    2) OR antecedent is therefore true, so a checking thread is spawned.
    3) ##1 grant requires grant at C41.
    4) grant is low at C41, so the consequent fails and the property FAILS at C41.
    5) A reader who thinks both sources must rise sees no trigger at all and reports a vacuous pass, which is the wrong verdict here.

    Answer

    Answer: FAIL at C41 - one rising side is enough to launch the check, and grant is missing one cycle after the req_b rise.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. One rising source is enough to start the check, and grant is missing at C41.

    Why candidates get it wrong

    The wrong reading ('OR needs both rises') starts no attempt and reports a green vacuous pass, hiding a real missing grant. Because an OR antecedent fires when either side is true, the req_b rise alone creates the obligation.

    Interviewer follow-up

    What changes if grant is high at C41, and what if neither request rises? Model answer: with grant high at C41 the C40 attempt is a real (non-vacuous) PASS. If neither request rose, no attempt starts and the property reports a VACUOUS-PASS, which proves nothing about the grant path.

    Say it out loud

    The antecedent is an or, so one rising source is enough. The rise of req_b at C40 starts the check, and grant must be high at C41. Grant is low at C41, so the property fails there. The trap is thinking both requests must rise, which starts no attempt and gives a green vacuous pass that hides a real missing grant. I would next add a cover on each side of the or.

    Related topics

    • $rose, $fell, $stable, $changed

    • Designing Good Antecedents

    • Back to Implication Puzzles

    • SVA Assertion Puzzles section

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    See also

    • Overlap vs Non-Overlap
    • Pure Vacuity
    • Chained Consequent With ##