Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
      • Overlap vs Non-Overlap
      • Pure Vacuity
      • Chained Consequent With ##
      • Non-Overlapped Window
      • throughout in Consequent
      • OR Antecedent Trigger
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
Loading lesson

←Implication Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Implication Puzzles
  5. Pure Vacuity
On this page

    VLSI DV Interview PuzzlesAll levels

    Pure Vacuity

    Property intent: every req must be granted within 0 to 2 cycles. In this test, req never becomes 1 (all samples 0). Determine the verdict.

    Puzzle

    Difficulty: Easy · Puzzle 2 of 6 · Topic: Implication Puzzles

    Property intent: every req must be granted within 0 to 2 cycles. In this test, req never becomes 1 (all samples 0). Determine the verdict.

    Code

    design.sv
    property p_vacuous;
      @(posedge clk) req |-> ##[0:2] gnt;
    endproperty

    Hint

    Ask whether the antecedent ever spawns a checking thread.

    Step-by-step solution

    Diagram
    1) req is never true at a sampled clock edge.
    2) No implication attempts are triggered.
    3) With no triggered antecedent, implication succeeds vacuously.

    Answer

    Answer: VACUOUS-PASS - antecedent never triggers, so no failing obligation is created.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. With req never high the property never fails and the antecedent cover never hits: the pass is vacuous.

    Why candidates get it wrong

    Vacuous pass is logically valid but dangerous if used as evidence of functional correctness without coverage. Some tools count it as a pass in the summary; look for the vacuous or non-vacuous split.

    Interviewer follow-up

    What companion cover/assert would you add to ensure this property is meaningfully exercised? Model answer: a cover property on the antecedent (cover property (@(posedge clk) req)) to prove the trigger happens, and ideally cover property (req ##[0:2] gnt) to prove a real non-vacuous pass; a regression with zero hits on either is a hole.

    Say it out loud

    With req never high, the antecedent never triggers, so no attempt is ever created and the property passes vacuously. That is logically valid but it proves nothing about grants. The trap is counting that green result as evidence of correctness. I would next look at the vacuous versus non-vacuous split, and add a cover on the antecedent so I know the test really sent a request.

    Related topics

    • Vacuous Success

    • Vacuous and Trivially True Assertions

    • Back to Implication Puzzles

    • SVA Assertion Puzzles section

    Previous

    118 / 293

    Next: Chained Consequent With ##

    Up next

    Up nextChained Consequent With ##

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Non-Overlapped Window
    • throughout in Consequent
    • OR Antecedent Trigger