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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
      • Overlap vs Non-Overlap
      • Pure Vacuity
      • Chained Consequent With ##
      • Non-Overlapped Window
      • throughout in Consequent
      • OR Antecedent Trigger
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Implication Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Implication Puzzles
  5. Non-Overlapped Window
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    VLSI DV Interview PuzzlesAll levels

    Non-Overlapped Window

    Property intent: after req, grant may arrive in the next cycle or one cycle after that (the window is counted after the |=> shift). Timeline (all other samples are 0): C20 req=1, C21 gnt=0, C22 gnt=1. Determine the verdict.

    Puzzle

    Difficulty: Medium · Puzzle 4 of 6 · Topic: Implication Puzzles

    Property intent: after req, grant may arrive in the next cycle or one cycle after that (the window is counted after the |=> shift). Timeline (all other samples are 0): C20 req=1, C21 gnt=0, C22 gnt=1. Determine the verdict.

    Code

    design.sv
    property p_nonoverlap_range;
      @(posedge clk) req |=> ##[0:1] gnt;
    endproperty

    Hint

    Because of |=>, the ##[0:1] window starts one cycle after req, so it ends one cycle later than you may expect.

    Step-by-step solution

    Diagram
    1) req at C20 triggers non-overlapped consequent starting at C21.
    2) ##[0:1] allows gnt at C21 or C22.
    3) gnt is low at C21 but high at C22, the last legal cycle, so the consequent matches.
    4) With |-> instead the window would be C20..C21 and this grant would be too late.

    Answer

    Answer: PASS - with |=>, the search window is C21 to C22, and gnt arrives at C22, the last legal cycle.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. |=> shifts the window to C21..C22 so gnt at C22 passes; the same range after |-> would be C20..C21 and fail.

    Why candidates get it wrong

    The grant is on the very last legal cycle. Forgetting the |=> shift gives window C20..C21 and a false FAIL; double-counting the shift gives C23 and lets a late grant slip through. The waveform has gnt only at C22 so that exactly one of those readings fails.

    Interviewer follow-up

    Would the same waveform pass or fail if the operator were |-> instead of |=>? Model answer: FAIL, reported at C21. |-> ##[0:1] gnt looks at C20 and C21, and gnt is low at both; the C22 grant is outside the window. (If gnt were high at C21, both operators would pass, which is why this waveform uses C22.)

    Say it out loud

    With the non-overlapped arrow the search starts one cycle after req, so the window is C21 to C22. Gnt is low at C21 and high at C22, the last legal cycle, so the property passes. The trap is forgetting the shift, which gives C20 to C21 and a false failure, or counting the shift twice and letting a late grant through. I would check the boundary by moving the grant to C23 and confirming it fails.

    Related topics

    • |-> vs |=>

    • Cycle Delays: ##N and ##[M:N]

    • Back to Implication Puzzles

    • SVA Assertion Puzzles section

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    See also

    • Overlap vs Non-Overlap
    • Pure Vacuity
    • OR Antecedent Trigger