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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
    • DPI-C: Calling C from SystemVerilog
    • bind: Attaching Verification to RTL
    • Macros, Defines & Compilation
    • Plusargs, Files & Runtime Configuration
      • $test$plusargs & $value$plusargs
      • File I/O
      • Config Architecture: Files vs Plusargs vs Objects
      • Wave Dumping & Runtime Control
    • Simulation Performance & TB Memory
    • RTL/TB Boundaries, Races & Timing
    • What the Open Simulators Run
  • Senior & Interview Preparation23
  • Principal-Level Verification34
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←Advanced Language & Integration
  1. Topics
  2. SystemVerilog
  3. Advanced Language & Integration
  4. Plusargs, Files & Runtime Configuration

Part 7 of 9Part 7 of 9/Advanced & IntegrationIntermediate

Plusargs, Files & Runtime Configuration

One image, many runs: plusargs, files, config objects, memory images and wave control.

  • 4topics
  • 4lessons

One compiled image serves a whole regression. Plusargs select the test and tune its knobs, files carry stimulus and images in and logs and dumps out, and wave controls decide what gets recorded.

Diagram
TOPIC MAP — THE RUNTIME BOUNDARY

  build once                         run many times
  ──────────                         ──────────────
  compile + elaborate ──► simv ◄── +TESTNAME=smoke +VERBOSITY=HIGH
                            │  ◄── +PRELOAD=image.hex +WIN_START=9000000
                            │
            ┌───────────────┼────────────────┐
            │               │                │
            ▼               ▼                ▼
        plusargs        file I/O         wave control
        (lesson 1)      (lesson 2)       (lesson 4)
            │               │
            ▼               ▼
        config object   memory preload
        architecture    and dump compare
        (lesson 3)      (in lesson 2)

Lesson

You will build…

Path

Plusarg parsing

Existence vs value knobs, defaults and one registry.

Required

File I/O and memory images

Logs, line parsing, preload images and golden compares.

Recommended

Config architecture

Three layers, precedence and the central resolve function.

Required

Waves and runtime control

Dump windows, exit discipline and verbosity knobs.

Recommended

Required is the core first pass for this part's goal, Recommended is for most learners, and Optional is reference, specialist or revision material.

Check yourself A regression needs 500 transactions with waves off, then a rerun with waves around a failure. Which knobs change between the runs?

Only the wave knobs change: add +WAVES with a start and stop around the failure time. The test name, transaction count and seed stay identical, so the failure reproduces inside the window.

“How do you configure one image for a thousand tests without recompiling?” A strong answer names plusargs for knobs, files for data, one central parse with a printed banner, and plusarg-gated dumps for debug.

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See also

  • DPI-C: Calling C from SystemVerilog
  • bind: Attaching Verification to RTL
  • Macros, Defines & Compilation