The SystemVerilog preprocessor runs before the compiler sees the code. ` define`, ifdef` and include`` do pure text substitution with no type checking and no scope.
When would I use this? When you write a log macro that adds file and line, a switch that turns checks on only in simulation, or a shared include file that many files pull in. You will also read other people's macros long before you write your own, so the debugging lesson pays off early.
TOPIC MAP — PREPROCESSOR TO SIMULATOR
source.sv ──► PREPROCESSOR ──► expanded text ──► COMPILER ──► ...
│
┌────────────┼──────────────┐
│ │ │
▼ ▼ ▼
`define `ifdef `include
text macros conditional file paste
(lesson 1) compilation + guards
(lesson 2) (lesson 3)
│ │ │
└────────────┴──────────────┘
│
▼
Debugging macro problems (lesson 4:
expansion errors, loud guards, safe
log macros, build stages)Lesson | Covers | Path |
|---|---|---|
Object-like and function-like macros, the parens rule, multiline bodies, and macros versus parameters. | Recommended | |
` | Recommended | |
Textual paste semantics, the double-include failure, the guard pattern, and search paths. | Optional | |
Expansion-error reading, loud configuration guards, a safe log macro, and build stages. | Optional |
Required is the core first pass for this part's goal, Recommended is for most learners, and Optional is reference, specialist or revision material.
A missing command-line define (` ifdef`` on a misspelled or unset name is silently false), or a macro redefined later in compile order so the second build expands a different body.