You rerun synthesis, change one number, and the netlist is different. Which number was it, what did the tool do with it, and what did you get for the extra area? This lesson answers with a real run, not a sketch.
The design below is a small decoder: a 12-bit input, one output built from AND-OR terms and one from parity. It is only big enough to show the effect and small enough to draw. The script synthesizes it once, saves the generic gates, then maps the same gates five times with a different delay target -D, in picoseconds, against sized.lib. That library offers each cell in three sizes: plain, _X2 and _X4, where a bigger cell is faster and larger.
read_verilog <<EOV
module decode (input [11:0] x, output y, output z);
assign y = ((x[0] & x[1]) | (x[2] & x[3] & x[4]) | (x[5] ^ x[6]) | (x[7] & ~x[8])) & (x[9] | x[10] | ~x[11]);
assign z = ^x[7:0] ^ (x[8] & x[9]);
endmodule
EOV
synth -top decode -flatten
design -save generic
tee -o abc_1000.txt abc -liberty sized.lib -constr typical.constr -D 1000
tee -o stat_1000.txt stat -liberty sized.lib
write_json net_1000.json
select -assert-none t:*_X2 t:*_X4
design -load generic
tee -o abc_800.txt abc -liberty sized.lib -constr typical.constr -D 800
tee -o stat_800.txt stat -liberty sized.lib
design -load generic
tee -o abc_700.txt abc -liberty sized.lib -constr typical.constr -D 700
tee -o stat_700.txt stat -liberty sized.lib
design -load generic
tee -o abc_600.txt abc -liberty sized.lib -constr typical.constr -D 600
tee -o stat_600.txt stat -liberty sized.lib
write_json net_600.json
select -assert-min 1 t:*_X2 t:*_X4 %u
design -load generic
tee -o abc_400.txt abc -liberty sized.lib -constr typical.constr -D 400
tee -o stat_400.txt stat -liberty sized.lib
design -load generic
tee -o abc_one_size.txt abc -liberty course.lib -constr typical.constr -D 400
tee -o stat_one_size.txt stat -liberty course.lib
log PASS: a tighter delay target upsizes cells that a loose target leaves at size 1In a commercial flow the target comes from the clock: create_clock -period 0.7 asks for 700 ps per cycle, which must also cover clock-to-q, setup, and uncertainty on top of the combinational delay. Yosys and ABC take the combinational slice directly as -D 700. Both hand the mapper one number to meet. ABC also needs the drive on each input and the load on each output, which typical.constr gives it (a BUF driver on the inputs and 0.05 pF of load on every output).
The same one. The 600 ps run already uses every size that helps (area 81, delay 594 ps), and the 400 ps run returns exactly those figures. A target tighter than the library allows buys nothing; the run table shows it.
Target -D | Cells | Area | Delay reached | Cells upsized |
|---|---|---|---|---|
1000 ps | 18 | 65 | 750 ps | 0 |
800 ps | 18 | 65 | 750 ps | 0 |
700 ps | 18 | 73 | 671 ps | 1 |
600 ps | 18 | 81 | 594 ps | 2 |
400 ps | 18 | 81 | 594 ps | 2 |
Read the table top to bottom. At 1000 and 800 ps the loose netlist already meets the target, so ABC stops at area 65 and 750 ps. At 700 ps it misses, so it upsizes some cells: area 73, delay 671 ps. At 600 ps and below it has upsized the cells on the slow path: area 81, delay 594 ps. That is 25% more area for 21% less delay, and nothing more at 400 ps.
Below are the netlists at the two ends of the table, drawn from the write_json files the script saved. Same function, same inputs and outputs. The loose netlist is on top. Cells the mapper upsized are drawn in orange, and their labels end in X2 or X4.
The cell count and the structure barely moved. What changed is the size of the cells on the slow path. In this ABC script the trade takes the usual shape: the mapper rarely rewrites the logic to meet a tighter target; it first buys speed with drive strength.
The last run in the script maps the same logic against course.lib, where each cell exists in one size, with the same 400 ps target. It reaches area 65 and 750 ps, the loose result: there is nothing to upsize to. A constraint can only steer the tool among choices the library offers.
The delay target and the cell library (or the output load). This lesson varied the target. Either one steers the mapper, so either can change the result.
Tighten the target to 600 ps, as the table shows: area rises to 81 and delay falls to 594 ps. If a still tighter target changed nothing, as at 400 ps, you would learn the library has no faster cells to give, and you would look at the logic or the library instead.
Every number and picture on this page comes from one Yosys 0.69 run of the script shown, recorded by the course checker (scripts/tools/run-rtl-testbenches.mjs with COURSE=synth): ABC maps one decoder against the teaching library sized.lib at five delay targets, with a 0.05 pF output load. The libraries are fictional, with illustrative numbers like course.lib, so absolute values are teaching units; the shape of the trade, not the digits, is the point.