A netlist and its reports answer three questions: what cells were used, how much area they take, and where the longest path runs. The running example is a 4-bit adder that maps to 18 library cells against course.lib. This topic reads each report line by line on small designs with checked counts, and every number on the four lessons comes from a recorded Yosys run rather than a sketch.
Report | What it answers |
|---|---|
stat | How many cells of each type the design holds, and how many wires connect them. |
stat -liberty | How much area each cell type contributes, in library units of the named teaching library. |
ltp | How many gates sit on the longest topological path of a generic netlist, or of a mapped one once read_liberty loads the library. A bare mapped run reports zero: missing visibility, not an empty design. |
write_verilog plus read_verilog | Whether a structural netlist survives a write and read-back round trip with identical cell counts. |
You can open any stat report and read every line: wires, public wires, cells, the per-type rows and the chip area. You can build an area total from stat -liberty rows as count times cell area, and you know the total only compares within one library. You can count fanout from a netlist instead of guessing it from the RTL, and you flatten a hierarchy knowing the gates stay put. You read a mapped ltp zero as missing library visibility and reload with read_liberty before quoting a mapped depth, and you round-trip a written netlist before trusting the file.
Lesson | What it covers |
|---|---|
Cell counts by type and wire counts on a checked 4-bit adder, word-level to mapped. | |
Area in library units from real stat -liberty rows, course.lib against nand_only.lib. | |
Flattening, fanout counted from the recorded netlist, generated names, and constant pins. | |
Longest topological path with ltp on the generic netlist, the read_liberty fix for the mapped zero, and a delay ranking from recorded ABC runs, plus a write, read-back and recount loop. |
It tells cell area by type in library units of the named library, which the area lesson builds row by row. It tells nothing about wire area or placement, which appear only later in the flow.
This hub shows no new run. Every number on the four lessons below comes from a Yosys 0.69 run recorded by the course checker (scripts/tools/run-rtl-testbenches.mjs with COURSE=synth); the libraries are fictional, so absolute values are teaching units and only the reading method transfers.