Synthesis optimises against the constraints it is given: clocks set the target, input and output delays bound the IO paths, drive and load bound the port edges, and exceptions mark the paths that play by different rules. A missing constraint leaves its paths without a target, and an over-tight one spends area chasing a fiction. This topic rebuilds each of those ideas as a recorded run plus hand-derived arithmetic, with every number labelled by where it came from.
Constraint | What it tells the tool |
|---|---|
create_clock | The clock name and its EXAMPLE period, which sets the timing target. |
Uncertainty and latency | Margin for skew and jitter, and the delay from the source to the flop clock pin. |
set_input_delay, set_output_delay | How much of the period the outside world already consumes on each IO path. |
set_driving_cell, set_load | The drive behind each input and the capacitance on each output. |
Exceptions | False paths, multicycle paths, case analysis and maximum-delay bounds. |
Write a correct create_clock and create_generated_clock pair, naming the master source pin and the divided register pin.
Split a clock period into IO budgets with uncertainty, latency, clock-to-Q and setup in their right places.
Map set_driving_cell and set_load onto real constraint lines, converting library picofarads to tool femtofarads.
State the standard multicycle hold pairing, and tell a false path from a multicycle from a max-delay bound.
Spot a missing constraint mechanically and recognise an over-tight target from its area-against-delay plateau.
Lesson | What it covers |
|---|---|
A recorded divide-by-2 register, correct generated-clock SDC, and ideal against propagated clocks. | |
Uncertainty against latency and the three IO budgets with hand-derived timing bars. | |
One cone under two recorded loads, the drive and load lines, and the picofarad trap. | |
Standard hold pairing with an edge model, and which exception fits which path. | |
A recorded loose-to-past-the-wall sweep, a coverage checker, and a slack table. |
Nothing is reported for it: the tool cannot time a path it was given no target for, so it is optimised without one. Unconstrained paths are a closure risk, not a timing win. In a commercial flow check_timing, or report_checks -unconstrained, lists them; not run here.
This hub runs nothing; its flowchart is a drawing of the lesson structure. The evidence for each claim sits on the five lesson pages, each recorded with Yosys 0.70 and ABC and listed in that page's frame.