Logic synthesis turns RTL, constraints, and a cell library into a gate-level netlist plus reports. The same RTL gives different netlists under different constraints, as the constraints lesson proves on a recorded sweep; the other lessons vary the RTL or the flow instead, and each quotes its own recording.
Term | Meaning |
|---|---|
RTL | The register-transfer description of what the design does each clock cycle. |
Constraints | Timing and electrical targets the implementation must meet, such as the clock period. |
Cell library | The available gates and flops with their area and timing, here the teaching library course.lib. |
Netlist | The chosen cells and their wiring: the implementation carried forward. |
Reports | Cell counts, area by cell type, and timing figures describing the chosen netlist. |
After this topic you can read a synthesis run the way a tool reports it: name the stage each cell family belongs to, explain why the mapped netlist differs from the generic one, and predict what a tighter constraint would change before rerunning anything. A concrete example from the first lesson: the 4-bit saturating adder maps to 20 library cells at area 58 library units of course.lib, reaching 635 ps against a 1000 ps target. The lessons below build that reading skill in order, one recorded design at a time.
Lesson | What it covers |
|---|---|
Inputs, outputs, flow position, and area in library units. | |
Read, elaborate, optimise, map, and report, with a recorded stop after each. | |
One RTL under five delay targets: a recorded sweep of cell sizes, area, and delay. | |
A real Yosys flow on one design, with assertions pinning robust mapped facts. | |
Why commercial tools match these concepts with different command names. |
Inputs: RTL, constraints, and the cell library. Outputs: the gate-level netlist and its reports.
This hub page is orientation with one cited recording: the saturating adder from the first lesson maps to 20 library cells at area 58 library units of course.lib, reaching 635 ps against a 1000 ps target. The flowchart shows the teaching stage order and the lesson table points at recorded runs. The teaching libraries (course.lib and friends) are fictional with illustrative numbers, so absolute areas are teaching units; the stage boundaries are the point. Yosys 0.69+post throughout the topic.