Each RTL construct maps to specific hardware. Operators become word-level cells, complete selects become multiplexers, a skipped assignment in a combinational block becomes a latch, and clocked blocks become flip-flops. The five lessons below each prove one row of that mapping with a recorded tool run, so this hub is a map over evidence rather than a claim on its own.
Read the chart left to right whenever you meet unfamiliar RTL. First ask which row the block belongs to: is it an operator, combinational and complete, combinational with a gap, clocked, a pin driver, a counted loop, or testbench code wearing an RTL costume. The row names the cell family before any report is opened, which turns the later lessons from surprises into confirmations.
Lesson | What it covers |
|---|---|
Operators to word cells ($add, $eq, $mux) and then to bit cells, proved with the tool. | |
If chains, one-hot case selects, and their depth and area. | |
The missing-else latch, its fixes, and why always_comb refuses one. | |
Clocked blocks, pin tri-states, bus fights, and unrolled loops. | |
Delays, initial blocks, and the real-type boundary. |
One recorded number to set the tone: the latch lesson elaborates a bare 8-bit if without an else and records 1 $dlatch cell holding the bus whenever the enable drops, while each of the three fixed variants records zero. Every lesson below holds itself to the same bar: a number from a run, never an adjective.
The topic is finished when each of these is a reflex rather than a lookup. Every item is proved by the lesson named beside it, with the recorded cell counts on the page.
Name the word cell each operator infers, then read the bit-level count after techmap (Combinational Blocks Infer Logic).
Write one select two ways, prove the forms equivalent, and read which cost the mapper actually paid (Priority Chains versus Parallel Selects).
Remove a latch three different ways and watch the recorded $dlatch count fall to zero (Latch Inference from Incomplete Assignment).
Price a sync reset against an async reset from mapped reports instead of rules of thumb (Flops, Tri-States and Unrolled Loops).
Reject delays, testbench blocks and unelaboratable types from RTL by naming what the tool kept and what it ignored (What Is Not Synthesizable).
A latch. The latch lesson proves one $dlatch with the tool and contrasts it with a mux.
The hub shows one recorded figure: the bare 8-bit latch variant from the latch-inference run, a single highlighted $dlatch with no select cells beside it (Yosys 0.70+post through the course checker, COURSE=synth scripts/tools/run-rtl-testbenches.mjs). Each lesson below records its own run the same way; the flowcharts here only summarize those recordings. Library areas are teaching units from course.lib, so absolute values are illustrative and the cell families are the point.