This part turns an elaborated network into library cells. Boolean optimisation shrinks the network, then technology mapping covers it with cells for area or delay. The library sets each cell cost, and structuring repairs fanout, slew, and capacitance violations.
Topic | Lessons | Description | Time |
|---|---|---|---|
5 | Constant propagation, redundancy removal, sharing, and the depth-area trade-off. | 40 min | |
5 | Covering a Boolean network with library cells for area or delay. | 40 min | |
5 | Function, area, timing arcs, and delay tables in the course Liberty library. | 40 min | |
5 | Fanout, slew and capacitance rules and how synthesis repairs them. | 40 min |
One recorded run shows the whole part in miniature: the same design mapped for a loose and a tight delay target comes out at area 16 and 342.31 ps, then area 33.4 and 210.91 ps. The area against delay lesson records the full sweep.
The library sets every cost the mapper trades: area, arcs, tables, and drive limits. The Cell Libraries and Liberty topic shows which entries matter.