Same concepts, different commands

Every synthesis tool walks the same five stages, but each vendor names the steps differently and splits the work at different joints. One tool reads RTL with a command called read, another elaborates with elaborate, a third compiles the whole middle of the flow with a single compile, and all of them report area and timing with some flavour of report_area and report_timing. The names differ; the questions each step answers do not.

Nothing on this page is commercial-tool syntax, and nothing here runs anywhere but Yosys. The commercial names appear for orientation only, so that a reader meeting compile or report_area elsewhere recognises which stage they belong to. The only runnable vocabulary in this course is the Yosys passes in the script below, and the table maps each of those passes to its stage and to the commercial name for the same job.

The vocabulary run

The script reruns the AND-OR cone from the previous lesson through the full vocabulary: read the design in, elaborate it, optimise it, lower it, map it, and report it. Each stage writes its own recording, and the assertions pin the same shape the previous lesson proved: two $and cells plus one $or cell with zero generic gates before mapping, library cells only after.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

read_verilog <<EOV
module and_or(input a, b, c, d, output y);
assign y = (a & b) | (c & d);
endmodule
EOV
hierarchy -check -top and_or
proc
opt
tee -o stat_opt.txt stat
write_json net_opt.json
design -save vocab_opt
techmap
tee -o abc_vocab.txt abc -liberty course.lib -constr typical.constr -D 1000
tee -o stat_vocab.txt stat -liberty course.lib
write_json net_vocab.json
design -save vocab_mapped
design -load vocab_opt
select -assert-count 2 t:$and
select -assert-count 1 t:$or
select -assert-none t:$_AND_ t:$_OR_ t:$_NOT_ t:$_MUX_ t:$_XOR_ t:$fa %u
design -load vocab_mapped
select -assert-none t:$and t:$or t:$xor t:$mux t:$not t:$add t:$sub %u
select -assert-none t:$_AND_ t:$_OR_ t:$_NOT_ t:$_MUX_ t:$_XOR_ t:$_NAND_ t:$_NOR_ %u
select -assert-min 1 t:INV t:BUF t:NAND2 t:NOR2 t:AND2 t:OR2 t:NAND3 t:NOR3 t:XOR2 t:XNOR2 t:AOI21 t:OAI21 t:MUX2 %u
check
log PASS: one design shows every vocabulary word from read to report

The recording anchors the table that follows. After the coarse half of optimisation the netlist holds 3 word-level cells; after mapping it holds 3 library cells at area 6 library units of course.lib. Those two numbers are what the two vocabularies describe with different words: our stat -liberty report and their report_area output answer the same question, which cells at what area, about the same netlist.

The mapping table

Read the middle column as the stable concept and the outer columns as two dialects for it. Yosys spells elaboration as two passes, hierarchy and proc, where a commercial tool says one word, and it files the lowering pass techmap under optimisation because lowering is technology-independent; only abc maps. Neither dialect is more correct; they cut the same five stages at different joints, and the commercial column is never typed into a tool anywhere in this course. Those commercial names carry no options or flags here: vendors spell and split them differently, so look up the exact command in whatever tool you are using.

Agreement check, not a break-it: bundle the passes into one command

This variant checks agreement rather than breaking anything: commercial flows rarely expose five separate passes, and one compile does the middle of the flow in a single step. Yosys has its own bundle, the stock synth pass, so the second script reruns the same cone that way: one synth -top in place of the separate elaborate, optimise, and lower passes, followed by the same abc -liberty and stat -liberty. The assertions pin the same endpoint shape as before: no coarse or generic cells, library cells only.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

read_verilog <<EOV
module and_or(input a, b, c, d, output y);
assign y = (a & b) | (c & d);
endmodule
EOV
hierarchy -check -top and_or
synth -top and_or -flatten
tee -o stat_synth.txt stat
write_json net_synth.json
design -save after_synth
tee -o abc_compile.txt abc -liberty course.lib -constr typical.constr -D 1000
tee -o stat_compile.txt stat -liberty course.lib
write_json net_compile.json
design -save compiled
design -load compiled
select -assert-none t:$and t:$or t:$xor t:$mux t:$not t:$add t:$sub %u
select -assert-none t:$_AND_ t:$_OR_ t:$_NOT_ t:$_MUX_ t:$_XOR_ t:$_NAND_ t:$_NOR_ %u
select -assert-min 1 t:INV t:BUF t:NAND2 t:NOR2 t:AND2 t:OR2 t:NAND3 t:NOR3 t:XOR2 t:XNOR2 t:AOI21 t:OAI21 t:MUX2 %u
check
log PASS: one compile-like synth plus abc reaches the same library-only endpoint

The bundled run reaches the same endpoint, and that sameness is the point of the check: the cell total, area, and delay all match the explicit-passes run above. The stages did not vanish; synth ran its own elaborate, optimise, and lower sequence inside one command, exactly as a commercial compile would. The bundling is the dialect; the stages are the concept.

The misuse that stays inside one tool is subtler: reading a report_area printout as if it described the generic netlist. Area cannot describe word-level cells, because word-level cells have no library prices; the number on the page would then be attached to the wrong stage, and every decision built on it would price logic that was never built. When an area number appears, ask which netlist it prices first. On this page the answer is recorded: the mapped one, with its families listed in the stat report, never the generic one.

Common mistakes

Related topics

• What synthesis does

• Scripted Flows and Regression

• Equivalence Checking