Synthesis Foundations cover what logic synthesis does and where it sits in the chip flow, which RTL constructs infer which hardware, and how to read the netlists and reports the tool produces. Everything later in the course assumes these readings.
Topic | Lessons | Description | Time |
|---|---|---|---|
5 | What logic synthesis does and where it sits: RTL and constraints in, netlist and reports out. | 40 min | |
5 | Which RTL constructs infer which hardware, and the latch and priority pitfalls. | 40 min | |
4 | Cell counts, area by cell type, fanout, and the longest path from real reports. | 32 min |
Constraints steer optimisation and mapping, so a tighter target first buys bigger cells on the critical path, though ABC may also restructure the logic. The Synthesis Flow Overview topic shows the stages where that happens.