RISC-V Design · All levels
Privilege Levels, Execution Modes, and Delegation Boundaries: Theory Deep Dive
Theory Deep Dive for Privilege Levels, Execution Modes, and Delegation Boundaries.
Theory deep dive
Theory Deep Dive for Privilege Levels, Execution Modes, and Delegation Boundaries is anchored on Privilege-transition latency and number of unauthorized accesses blocked by PMP/page-permission checks per billion instructions.. Convert observations into mechanism-backed decisions with explicit ownership.
Theory matters when it predicts engineering outcomes. Tie abstract ISA and microarchitecture concepts to measurable behavior in trace and counter data.
Pipeline model
diagram
RISC-V PIPELINE DIAGRAM - Privilege Levels, Execution Modes, and Delegation Boundaries
PC -> IF -> ID -> EX -> MEM -> WB
| | | | |
i-cache decode ALU/BR LSU regfile write
\ |
+-> branch resolve + redirect
Hot paths:
- branch + load-use dependencies in ID/EX
- memory latency stretching MEM stage
- writeback arbitration for integer/vector units
Focus: keep control hazards predictablePrivilege model
diagram
PRIVILEGE MODE STACK - Privilege Levels, Execution Modes, and Delegation Boundaries
+------------------------------+
| Machine mode (M) |
| firmware, PMP, trap root |
+---------------+--------------+
|
delegated traps
v
+------------------------------+
| Supervisor mode (S) |
| kernel, page tables, drivers |
+---------------+--------------+
|
ecall / syscall
v
+------------------------------+
| User mode (U) |
| applications, libraries |
+------------------------------+
Key rule: each upward transition records cause + PC in trap CSRs.