RISC-V Design · All levels
RISC-V ISA Fundamentals
The RV32I and RV64I base model, instruction encoding discipline, register and calling conventions, and a practical map of the compressed and standard extension ecosystem.
Section goal
The RV32I and RV64I base model, instruction encoding discipline, register and calling conventions, and a practical map of the compressed and standard extension ecosystem.
How to study this section
Start with each topic hub to establish mechanism-first framing.
Use reports and debug pages to separate symptoms from root cause.
Practice worked examples and interview drills under fixed metadata.
Close with checklist and silicon impact before signoff claims.
Topics
base-integer-isa/ - Base Integer ISA (RV32I and RV64I) Execution Model
encoding-and-formats/ - Instruction Encoding and Format Families
registers-and-calling/ - Register Conventions and Calling Discipline
compressed-and-extensions-overview/ - Compressed ISA and Extension Landscape Overview