RISC-V Design · All levels
Memory & Virtualization
RISC-V virtual memory translation, precise page-fault handling, physical-memory protection, and IOMMU behavior for safe and performant CPU and DMA access.
Section goal
RISC-V virtual memory translation, precise page-fault handling, physical-memory protection, and IOMMU behavior for safe and performant CPU and DMA access.
How to study this section
Start with each topic hub to establish mechanism-first framing.
Use reports and debug pages to separate symptoms from root cause.
Practice worked examples and interview drills under fixed metadata.
Close with checklist and silicon impact before signoff claims.
Topics
mmu-tlb-walk/ - MMU, TLB Hierarchy, and Hardware Page-Table Walk
page-fault-handling/ - Page Fault Handling, Trap Flow, and Recovery Paths
pmp-and-physical-protection/ - PMP and Physical Memory Protection Domains
iommu-and-dma-view/ - IOMMU Translation and the DMA Memory View