RISC-V Design · All levels
RISC-V Design - Architecture to Silicon
Execution-focused RISC-V mastery from ISA and decode through pipeline, extensions, privilege, memory virtualization, verification, and SoC bring-up closure.
Course promise
This is the execution-focused RISC-V design course for silicon teams. It teaches how to reason from workload symptoms to mechanisms, then close design decisions with artifacts, owners, and rollback-safe criteria.
Translate RISC-V architecture concepts into measurable engineering decisions.
Diagnose decode, pipeline, privilege, memory, extension, and integration bottlenecks.
Connect architecture choices to performance, power, timing, and bring-up risk.
Use one framework: workload -> mechanism -> artifact -> owner -> decision.
Course map
ISA and software contract
-> decode and control intent
-> pipeline timing and hazards
-> extension and vector/crypto scaling
-> privilege, traps, and CSR model
-> MMU, TLB, and virtualization behavior
-> verification closure and SoC bring-upRelated topics
Full course index
Every section and lesson in this track — expand folders in the sidebar or jump from here.