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Privilege Levels, Execution Modes, and Delegation Boundaries: Debug Playbook

Debug Playbook for Privilege Levels, Execution Modes, and Delegation Boundaries.

Debug playbook

Debug Playbook for Privilege Levels, Execution Modes, and Delegation Boundaries is anchored on Privilege-transition latency and number of unauthorized accesses blocked by PMP/page-permission checks per billion instructions.. Convert observations into mechanism-backed decisions with explicit ownership.

  1. Freeze workload seed, binary, compiler, firmware, and platform setup.

  2. Find earliest persistent mechanism failure in the timeline.

  3. Build one reduced reproducer for dominant hypothesis.

  4. Patch minimal fix with explicit rollback gate.

  5. Rerun correctness + performance + power matrix.

Decision tree

diagram
ROOT CAUSE TREE - Privilege Levels, Execution Modes, and Delegation Boundaries

Privilege-transition latency and number of unauthorized accesses blocked by PMP/page-permission checks per billion instructions. regressed
          |
   reproducible on fixed seed?
      /                 \
    no                   yes
    |                     |
env/tool drift       first failing domain?
                     /        |         \
                  decode    execute    memory/MMU
                    |         |            |
               control map  bypass/FU   TLB/walk/perm
                    |
         privilege/CSR side effects checked?

Stop at first confirmed mechanism, then assign explicit owner + fix proof.

Review memo template

diagram
RISC-V REVIEW MEMO - Privileged Architecture / Privilege Levels, Execution Modes, and Delegation Boundaries

1. Symptom
   - Failing metric: Privilege-transition latency and number of unauthorized accesses blocked by PMP/page-permission checks per billion instructions.
   - Failing workload slice: <name>
   - Triggering mode: <privilege/virtualization/interrupt/cache/boot>
   - Build and runtime tags: <toolchain/firmware/RTL revision>

2. Mechanism hypothesis
   - Primary mechanism: RISC-V privileged architecture separates software responsibilities across machine mode (M), supervisor mode (S), and user mode (U), with optional hypervisor virtualization layering for host and guest control. M-mode owns platform bring-up and root control, while S-mode runs the operating system and U-mode executes applications under constrained permissions. Security and correctness hinge on explicit delegation and filtering: machine-level registers such as medeleg/mideleg can route selected traps to S-mode, while PMP and page-table permissions ensure each mode only touches approved address regions. Robust implementations also define deterministic rules for mode transitions during interrupts, exceptions, and system calls so return paths cannot leak privilege or corrupt architectural state.
   - Competing hypotheses: <decode control / hazard / MMU / privilege / integration>
   - Missing evidence: <trace/counter/proof/report>

3. Proposed action
   - Smallest reversible change: <RTL/compiler/runtime/config>
   - Expected movement: <throughput/latency/tail/perf-per-watt>
   - Regression risk: correctness, security, power, timing, software compatibility

4. Signoff
   - Required artifact: Privilege-transition matrix covering entry source, target mode, delegated cause bits, and required state-save set.
   - Required owners: CPU architecture lead, privileged ISA owner, firmware and boot owner, kernel porting owner, security validation owner
   - Final decision: ship, bounded rollout, rollback, or escalate
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