Privilege Levels, Execution Modes, and Delegation Boundaries: Interview Drills

PROMPT
You observe Privilege-transition latency and number of unauthorized accesses blocked by PMP/page-permission checks per billion instructions. on Privilege Levels, Execution Modes, and Delegation Boundaries. Walk through root cause and release decision.

STRONG ANSWER
1. Defines workload and earliest failing mechanism.
2. Explains mechanism: RISC-V privileged architecture separates software responsibilities across machine mode (M), supervisor mode (S), and user mode (U), with optional hypervisor virtualization layering for host and guest control. M-mode owns platform bring-up and root control, while S-mode runs the operating system and U-mode executes applications under constrained permissions. Security and correctness hinge on explicit delegation and filtering: machine-level registers such as medeleg/mideleg can route selected traps to S-mode, while PMP and page-table permissions ensure each mode only touches approved address regions. Robust implementations also define deterministic rules for mode transitions during interrupts, exceptions, and system calls so return paths cannot leak privilege or corrupt architectural state.
3. Requests proving artifact: Privilege-transition matrix covering entry source, target mode, delegated cause bits, and required state-save set.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Suggests generic optimization ideas without mechanism proof or owner accountability.

RISC-V EVIDENCE MATRIX - Privilege Levels, Execution Modes, and Delegation Boundaries

+--------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                 | Tells you                      | Does not prove                 | Next action               |
+--------------------------+--------------------------------+--------------------------------+---------------------------+
| perf counter timeline    | where regression appears       | exact mechanism causality      | correlate with trace      |
| decode/control dump      | control intent per instruction | pipeline side-effect ordering  | inspect retire semantics  |
| trap + CSR logs          | privilege/fault behavior       | performance bottleneck alone   | pair with CPI buckets     |
| MMU/TLB walk trace       | translation behavior           | full system QoS impact         | test mixed workloads      |
| post-fix trend graph     | movement after fix             | long-term stability            | run stress matrix         |
+--------------------------+--------------------------------+--------------------------------+---------------------------+