RISC-V Design · All levels

Pipeline Performance and CPI Decomposition: Theory Deep Dive

Theory Deep Dive for Pipeline Performance and CPI Decomposition.

Theory deep dive

Theory Deep Dive for Pipeline Performance and CPI Decomposition is anchored on Measured CPI broken into ideal base CPI, structural stalls, data stalls, control stalls, and memory wait contributions.. Convert observations into mechanism-backed decisions with explicit ownership.

Theory matters when it predicts engineering outcomes. Tie abstract ISA and microarchitecture concepts to measurable behavior in trace and counter data.

Pipeline model

diagram

RISC-V PIPELINE DIAGRAM - Pipeline Performance and CPI Decomposition

PC -> IF -> ID -> EX -> MEM -> WB
      |     |      |      |      |
  i-cache decode  ALU/BR  LSU    regfile write
              \   |
               +-> branch resolve + redirect

Hot paths:
  - branch + load-use dependencies in ID/EX
  - memory latency stretching MEM stage
  - writeback arbitration for integer/vector units

Focus: keep control hazards predictable

Privilege model

diagram

PRIVILEGE MODE STACK - Pipeline Performance and CPI Decomposition

            +------------------------------+
            | Machine mode (M)             |
            | firmware, PMP, trap root     |
            +---------------+--------------+
                            |
                    delegated traps
                            v
            +------------------------------+
            | Supervisor mode (S)          |
            | kernel, page tables, drivers |
            +---------------+--------------+
                            |
                    ecall / syscall
                            v
            +------------------------------+
            | User mode (U)                |
            | applications, libraries      |
            +------------------------------+

Key rule: each upward transition records cause + PC in trap CSRs.

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