RISC-V Design · All levels
Pipeline Implementation: Tricky Q&A
Senior interview and review questions for Pipeline Implementation.
Section Q&A bank
Use these drills after completing all topics in Pipeline Implementation. Answer with workload framing, mechanism proof, owner, and release decision.
Why can a five-stage pipeline still fail timing even when each stage seems logically balanced?
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[INT][RISCV][PIPELINE-IMPLEMENTATION]
Q: Why can a five-stage pipeline still fail timing even when each stage seems logically balanced?
A:
Logical balance is only part of closure. Real timing includes register setup/clock skew, mux depth from forwarding, decode fanout, and routing delay that can concentrate unexpectedly in one stage boundary. If stage contracts do not constrain where control generation and exception tagging happen, logic drifts and critical paths emerge late. Timing-safe design requires explicit per-stage budgets and periodic synthesis/PnR feedback, not just architectural stage names.
FOLLOW-UP TRAP: Assuming IF/ID/EX/MEM/WB labels alone guarantee frequency scalability.When does forwarding solve a RAW dependency, and when must the pipeline stall instead?
diagram
[INT][RISCV][PIPELINE-IMPLEMENTATION]
Q: When does forwarding solve a RAW dependency, and when must the pipeline stall instead?
A:
Forwarding works when the producer value is already computed and available on a bypass source before the consumer operand is needed in EX. It cannot fix cases where data is not ready yet, most notably load-use dependencies when memory data returns too late for the next cycle's EX input timing. In those cases hazard logic must hold upstream stages and inject a bubble while preserving instruction order and kill semantics.
FOLLOW-UP TRAP: Treating every RAW hazard as bypassable regardless of value-ready timing.What is the minimum correctness guarantee for branch flush logic in an in-order core?
diagram
[INT][RISCV][PIPELINE-IMPLEMENTATION]
Q: What is the minimum correctness guarantee for branch flush logic in an in-order core?
A:
No wrong-path instruction may commit architected state: no register writes, no memory stores, and no visible CSR side effects. Redirect must also preserve precise traps, meaning exception reporting still reflects the oldest faulting instruction in program order. This requires kill propagation that dominates downstream write enables and store-commit conditions across all flush-plus-stall race scenarios.
FOLLOW-UP TRAP: Checking only PC redirect while ignoring side-effect suppression on younger instructions.How should CPI analysis guide pipeline changes without causing misleading conclusions?
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[INT][RISCV][PIPELINE-IMPLEMENTATION]
Q: How should CPI analysis guide pipeline changes without causing misleading conclusions?
A:
CPI must be decomposed into causal buckets with hardware counters and correlated to workload phases, then evaluated together with achieved clock frequency. A design tweak that reduces one stall class may increase another or lower Fmax, so total performance must be computed as instruction count times CPI divided by frequency. Reliable decisions come from benchmark suites and counter validation, not single microbench results.
FOLLOW-UP TRAP: Optimizing one CPI component in isolation without re-evaluating end-to-end performance.