RISC-V Design · All levels
PMP and Physical Memory Protection Domains: Step-by-Step Walkthrough
Step-by-Step Walkthrough for PMP and Physical Memory Protection Domains.
Step-by-step walkthrough
Step-by-Step Walkthrough for PMP and Physical Memory Protection Domains is anchored on Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests.. Convert observations into mechanism-backed decisions with explicit ownership.
Define failing workload and acceptance threshold.
Capture reproducible metadata and evidence snapshot.
Classify dominant mechanism path.
Propose minimal reversible change.
Validate cross-workload and corner behavior.
Document owner and rollout decision.
Reference path
diagram
RISC-V PIPELINE DIAGRAM - PMP and Physical Memory Protection Domains
PC -> IF -> ID -> EX -> MEM -> WB
| | | | |
i-cache decode ALU/BR LSU regfile write
\ |
+-> branch resolve + redirect
Hot paths:
- branch + load-use dependencies in ID/EX
- memory latency stretching MEM stage
- writeback arbitration for integer/vector units
Focus: keep control hazards predictable