PMP and Physical Memory Protection Domains: Mechanism

Mechanism to understand

Mechanism for PMP and Physical Memory Protection Domains is anchored on Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests.. Convert observations into mechanism-backed decisions with explicit ownership.

RISC-V Physical Memory Protection (PMP) constrains physical-address access by privilege mode using programmable regions and R/W/X permission bits, commonly in NAPOT or TOR encodings. Each memory access is checked against ordered PMP entries, enabling machine-mode firmware to isolate supervisor/user domains, secure monitors, and device windows before virtual translation or after it depending on implementation stage. Correct deployment requires deterministic region priority, lock-bit strategy, and synchronization with boot-time memory map handoff so protections cannot be bypassed by stale configuration or unexpected privilege transitions. In safety and security signoff, PMP policy must be validated alongside trap handling, debug access policy, and firmware update flows to prevent escalation paths.

• Name first failing path and trigger condition.

• Prove path loss with one measurable artifact.

• Assign owner who can deliver smallest reversible fix.

Pipeline mechanism sketch

RISC-V PIPELINE DIAGRAM - PMP and Physical Memory Protection Domains

PC -> IF -> ID -> EX -> MEM -> WB
      |     |      |      |      |
  i-cache decode  ALU/BR  LSU    regfile write
              \   |
               +-> branch resolve + redirect

Hot paths:
  - branch + load-use dependencies in ID/EX
  - memory latency stretching MEM stage
  - writeback arbitration for integer/vector units

Focus: keep control hazards predictable

Decode intent map

DECODE CONTROL MAP - PMP and Physical Memory Protection Domains

opcode/funct3/funct7      controls asserted
-----------------------   ---------------------------------------
LUI / AUIPC               rd_write, imm_select(U), alu_add_pc
JAL / JALR                rd_write, pc_redirect, link_write
BRANCH                    cmp_enable, branch_type, pc_redirect
LOAD                      mem_read, rd_write, wb_sel(memory)
STORE                     mem_write, store_size, addr_calc
OP-IMM                    alu_enable, imm_select(I), rd_write
OP                        alu_enable, src2_reg, rd_write
SYSTEM / CSR              csr_readwrite, trap_check, privilege_gate
VECTOR (V extension)      vdecode, lane_mask, vtype_update