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PMP and Physical Memory Protection Domains: Interview Drills
Interview Drills for PMP and Physical Memory Protection Domains.
Interview drills
Interview Drills for PMP and Physical Memory Protection Domains is anchored on Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests.. Convert observations into mechanism-backed decisions with explicit ownership.
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PROMPT
You observe Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests. on PMP and Physical Memory Protection Domains. Walk through root cause and release decision.
STRONG ANSWER
1. Defines workload and earliest failing mechanism.
2. Explains mechanism: RISC-V Physical Memory Protection (PMP) constrains physical-address access by privilege mode using programmable regions and R/W/X permission bits, commonly in NAPOT or TOR encodings. Each memory access is checked against ordered PMP entries, enabling machine-mode firmware to isolate supervisor/user domains, secure monitors, and device windows before virtual translation or after it depending on implementation stage. Correct deployment requires deterministic region priority, lock-bit strategy, and synchronization with boot-time memory map handoff so protections cannot be bypassed by stale configuration or unexpected privilege transitions. In safety and security signoff, PMP policy must be validated alongside trap handling, debug access policy, and firmware update flows to prevent escalation paths.
3. Requests proving artifact: PMP region map with rule-priority table, lock policy, and privilege-mode access matrix.
4. Proposes bounded fix + owner + rollback-safe validation.
WEAK ANSWER
Suggests generic optimization ideas without mechanism proof or owner accountability.Decision matrix
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RISC-V EVIDENCE MATRIX - PMP and Physical Memory Protection Domains
+--------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence | Tells you | Does not prove | Next action |
+--------------------------+--------------------------------+--------------------------------+---------------------------+
| perf counter timeline | where regression appears | exact mechanism causality | correlate with trace |
| decode/control dump | control intent per instruction | pipeline side-effect ordering | inspect retire semantics |
| trap + CSR logs | privilege/fault behavior | performance bottleneck alone | pair with CPI buckets |
| MMU/TLB walk trace | translation behavior | full system QoS impact | test mixed workloads |
| post-fix trend graph | movement after fix | long-term stability | run stress matrix |
+--------------------------+--------------------------------+--------------------------------+---------------------------+