RISC-V Design · All levels

PMP and Physical Memory Protection Domains

Memory & Virtualization: RISC-V Physical Memory Protection (PMP) constrains physical-address access by privilege mode using programmable regions and R/W/X permission bits, commonly in NAPOT or TOR encodings. Each memory access is checked against ordered PMP entries, enabling machine-mode firmware to isolate supervisor/user domains, secure monitors, and device windows before virtual translation or after it depending on implementation stage. Correct deployment requires deterministic region priority, lock-bit strategy, and synchronization with boot-time memory map handoff so protections cannot be bypassed by stale configuration or unexpected privilege transitions. In safety and security signoff, PMP policy must be validated alongside trap handling, debug access policy, and firmware update flows to prevent escalation paths.

What this topic teaches

PMP and Physical Memory Protection Domains trains mechanism-first reasoning for RISC-V design closure. RISC-V Physical Memory Protection (PMP) constrains physical-address access by privilege mode using programmable regions and R/W/X permission bits, commonly in NAPOT or TOR encodings. Each memory access is checked against ordered PMP entries, enabling machine-mode firmware to isolate supervisor/user domains, secure monitors, and device windows before virtual translation or after it depending on implementation stage. Correct deployment requires deterministic region priority, lock-bit strategy, and synchronization with boot-time memory map handoff so protections cannot be bypassed by stale configuration or unexpected privilege transitions. In safety and security signoff, PMP policy must be validated alongside trap handling, debug access policy, and firmware update flows to prevent escalation paths.

Senior-engineer framing question

When Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests. moves, can you isolate first failing mechanism, request decisive evidence, assign owner, and decide release-safe action?

diagram

RISC-V PIPELINE DIAGRAM - PMP and Physical Memory Protection Domains

PC -> IF -> ID -> EX -> MEM -> WB
      |     |      |      |      |
  i-cache decode  ALU/BR  LSU    regfile write
              \   |
               +-> branch resolve + redirect

Hot paths:
  - branch + load-use dependencies in ID/EX
  - memory latency stretching MEM stage
  - writeback arbitration for integer/vector units

Focus: map symptom to first failing stage

Architecture visuals

Draw before you tune. Use these visuals in design reviews, interview loops, and post-silicon triage.

Decode and control map

diagram

DECODE CONTROL MAP - PMP and Physical Memory Protection Domains

opcode/funct3/funct7      controls asserted
-----------------------   ---------------------------------------
LUI / AUIPC               rd_write, imm_select(U), alu_add_pc
JAL / JALR                rd_write, pc_redirect, link_write
BRANCH                    cmp_enable, branch_type, pc_redirect
LOAD                      mem_read, rd_write, wb_sel(memory)
STORE                     mem_write, store_size, addr_calc
OP-IMM                    alu_enable, imm_select(I), rd_write
OP                        alu_enable, src2_reg, rd_write
SYSTEM / CSR              csr_readwrite, trap_check, privilege_gate
VECTOR (V extension)      vdecode, lane_mask, vtype_update

Privilege stack

diagram

PRIVILEGE MODE STACK - PMP and Physical Memory Protection Domains

            +------------------------------+
            | Machine mode (M)             |
            | firmware, PMP, trap root     |
            +---------------+--------------+
                            |
                    delegated traps
                            v
            +------------------------------+
            | Supervisor mode (S)          |
            | kernel, page tables, drivers |
            +---------------+--------------+
                            |
                    ecall / syscall
                            v
            +------------------------------+
            | User mode (U)                |
            | applications, libraries      |
            +------------------------------+

Key rule: each upward transition records cause + PC in trap CSRs.

Translation path

diagram

MMU PAGE WALK DIAGRAM - PMP and Physical Memory Protection Domains

virtual address
    |
    +--> TLB lookup hit? ---- yes ---> physical address -> cache/memory
    |             |
    |             no
    v
satp root PPN + VPN indices
    |
    +--> level-2 PTE fetch (valid?)
    |         |
    |         +-- no -> page fault trap
    v
level-1 PTE fetch -> level-0 PTE fetch
    |
    +--> permissions check (R/W/X, U/S, A/D)
             |
             +-- fail -> access fault trap
             +-- pass -> install TLB entry -> continue

Vector lane lens

diagram

VECTOR LANE VIEW - PMP and Physical Memory Protection Domains

VLEN register file
   |
   +--> lane0: ALU/MUL/permute
   +--> lane1: ALU/MUL/permute
   +--> lane2: ALU/MUL/permute
   +--> lane3: ALU/MUL/permute
            ...
mask register -> per-lane predicate enable
load/store unit -> strided/segmented access queue

Throughput model:
effective ops/cycle = active_lanes * issue_rate * mask_density

Focus: balance lane utilization and memory feed

Ownership layers

diagram

RISC-V OWNERSHIP LAYERS - PMP and Physical Memory Protection Domains

layer                  owner                         closure artifact
--------------------   ----------------------------  -----------------------------
ISA compliance         architecture/spec team        unpriv + priv test evidence
decode/control         front-end RTL owner           decode matrix + assertions
pipeline timing        microarchitecture owner       hazard/perf regression trends
memory + MMU           LSU/MMU owner                 TLB/pagewalk trace checks
privilege/CSR path     firmware + kernel interface   trap/interrupt conformance
vector subsystem       vector RTL + compiler owner   lane-utilization profiles

Evidence required

Primary metric: Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests..
Primary artifact: PMP region map with rule-priority table, lock policy, and privilege-mode access matrix..
Owners to include: security architecture owner, firmware and boot-flow owner, CPU privilege architect, platform software owner, security validation owner.
One reproducible workload and one stable comparator run.
One run with locked environment metadata for causal confidence.

Root-cause tree

diagram

ROOT CAUSE TREE - PMP and Physical Memory Protection Domains

Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests. regressed
          |
   reproducible on fixed seed?
      /                 \
    no                   yes
    |                     |
env/tool drift       first failing domain?
                     /        |         \
                  decode    execute    memory/MMU
                    |         |            |
               control map  bypass/FU   TLB/walk/perm
                    |
         privilege/CSR side effects checked?

Stop at first confirmed mechanism, then assign explicit owner + fix proof.

Movement trend

diagram

BEFORE / AFTER TREND - PMP and Physical Memory Protection Domains

Unauthorized-access block rate, PMP rule evaluation latency, and coverage of privilege-domain isolation tests.
  ^
  |                           o target band
  |                    o after fix + reruns
  |             o
  |      o baseline (failing)
  +--------------------------------------------------> iteration
       capture issue      isolate mechanism      close + monitor

Use this view to confirm the gain is causal and stable across seeds.

Key takeaways

Classify mechanism before proposing fixes.
Tie every claim to one proving artifact.
Close with owner accountability and rollback criteria.

Common pitfalls

Averaging away tail behavior and mode-specific failures.
Blending results from mismatched build/runtime metadata.
Declaring closure before cross-workload validation.

Practice this lesson