PCIe/CXL Deep Dive · All levels

Speed and Width Negotiation: Interview Drills

Interview Drills for Speed and Width Negotiation.

Interview drills

Interview Drills for Speed and Width Negotiation focuses on Negotiated link speed, active lane count, and downgrade event frequency. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

diagram

PROMPT
You observe Negotiated link speed, active lane count, and downgrade event frequency on Speed and Width Negotiation. Explain root cause and release decision.

STRONG ANSWER
1. Defines failing traffic context and first transition loss.
2. Explains mechanism: Devices advertise supported speeds and lane widths via training fields. The link trains to the highest common mode; width degradation from lane failures reduces bandwidth and may change skew requirements.
3. Requests proving artifact: Link capability vs negotiated status register snapshot
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Gives generic PCIe tuning ideas without command evidence, owner accountability, or risk controls.

Interview evidence matrix

diagram

PCIe/CXL EVIDENCE MATRIX - Speed and Width Negotiation

+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                      | Tells you                      | Does not prove                 | Next action               |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| TLP type mix + credit stall counters    | protocol-layer stall cost    | link integrity and replay behavior   | inspect training margins  |
| queue age + class breakdown   | fairness and starvation risk   | command legality details       | parse command timeline    |
| LTSSM timeline + ordered set progression | timing-window pressure         | root cause by itself           | correlate with topology map|
| eye / Vref / skew snapshots   | PHY margin and drift behavior  | controller policy quality      | pair with schedule logs   |
| CE/UE + scrub telemetry       | reliability trajectory         | immediate perf bottleneck only | map to hotspot apcieesses  |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+

PCIe/CXL deep dive

LTSSM and equalization determine whether high-speed links are stable under corner traffic and retimer paths.

Concept diagram

diagram

LTSSM + EQ

Detect -> Polling -> Config -> L0 <-> Recovery

Metric graph

diagram

LINK INSTABILITY SOURCES

EQ margin           ██████
retimer FW          ████
SI/cable plant      ███

Reports and artifacts

LTSSM state log
EQ coefficient dump
negotiated speed/width snapshot
recovery trigger timeline

Mini case study

Gen5 passed cold boot EQ but entered Recovery loops under DMA heat after retimer firmware update.

Debug branches

Capture ordered sets at failure boundary
Compare EQ presets across temperature corners
Bypass retimer to isolate segment faults

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Key takeaways

Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.

Interview answer expansion

Strong interview answers for Speed and Width Negotiation start with workload framing and metric framing, then explain mechanism plainly: Devices advertise supported speeds and lane widths via training fields. The link trains to the highest common mode; width degradation from lane failures reduces bandwidth and may change skew requirements.

Then propose a measurement plan: TLP routing, credit dynamics, turnaround cost, RAS interference, and PHY margin where relevant.

Finally, present one bounded fix plus regression risk. PCIe/CXL interviews reward explicit tradeoff ownership, not generic tuning slogans.

Practice this lesson